What are STC Registers Correct Offsets?

[GBL2006]

Dear all,

I found some of the STC registers' addresses (offset) defined in the DDK kit (tstc.h) and in the document "DAQ-STC Technical Reference Manual" are in consistent, here is the list:

Register         

[GBL2006]

Oops!

Sorry, the preceeding message isn't complete.

I found the offsets for some of the STC registers are not same in the tSTC.h and in the document "DAQ-STC Technical Reference Manual".

List is here:

Register                   Offset in tSTC.h                    Offset in The Manual

AI_Command_2       0x08                                      0x04

AI_Status_1              0x04                                      0x02

AI_Status_2              0x0a                                      0x05

AO_Command_2     0x0a                                      0x05

AO_Status_1            0x06                                      0x03

AO_Status_2            0x0c                                      0x06

DIO_Parallel_Input   0x0e                                      0x07

G0_Command          0x0c                                      0x06

G1_Command          0x0e                                      0x07

G_Status                   0x08                                      0x04

Interrupt_A_ACK       0x04                                      0x02

Interrupt_B_ACk        0x06                                      0x03

Could someone tell me which one is correct please?

Thanks a lot for any help.

Best regards,

George 

[GBL2006]

Hi, all

And I checked the offsets in the tSTC.h file, found that:

AI_Command_1, AI_Command_2, G0_HW_Save and G_Status, four registers use same offset 0x08;

AI_SI_Load_A, DIO_Parallel_Input, G1_Command and G1_Save, four registers use same offset 0x0e;

AI_Status_2, AO_Command_2, DIO_Output and G1_HW_Save, four registers use same offset 0x0a;

AI_Mode_1, AO_Status_2, G0_Command and G0_Save, four registers use same offset 0x0c;

I don't understand how to distinguish the registers using same address. I knew that two registers can have same address only when one is write only and the other one is read only.

Please help

Thanks

Best regards,

George

[DiegoF]

Hi George,

Both offsets are correct!.  let me explain...

The difference between the two is the access mode.  Section 2.6.2, briefly mentions that the stc registers can be accessed using direct or windowed access (or a combination).  The access mode depends on the implementation.  For ESeries devices (and i think all other stc based devices), register with addresses below 16 are accessed using direct io.  All others are windowed.

The note in appendix B explains the offsets for the two addressing modes.  For windowed registers the addresses are in terms of 16-bit words.  For direct access, use 8-bit words.  The STC manual lists all register offsets using windowed access.

In the tSTC.h file, the base class of the register is the IO strategy.  Windowed registers inherit from tReg16IOWindowed16, direct register use tReg16IODirect16.  For example, AI_Command_1 and AI_Command_2 have the same offset in the h file, but use different io strategies:

class tAI_Command_2 : public tReg16IODirect16

class tAI_Command_1 : public tReg16IOWindowed16

Hope this helps,
Diego

[GBL2006]

Thanks, Diego

Quite frankly, I couldn't see the difference between the offsets for the two access modes. Here is my understanding, correct me if I am wrong.

1. IO direct mode: The actual address of a register is the Base Address of STC + offset (OFFSET_direct), the data will be written to / read from the address directly.

2. Windowed mode: Two special registers are used for the writting /reading data to/from the target register indirectly. The offset (OFFSET_windowed) of the target register will be sent to the Windowed Address Register (kAddressOffset = 0 as defined in tSTC.h) and the data will be written or read to/ from the Windowed Data Register (kDataOffset = 2 as defined in tSTC.h) .

3. Why the OFFSET_direct is different from OFFSET_window for the same register?

4. From the following code, I don't know why the "offset" should be different.

inline void tSTC::tReg16IODirect16::write( tBusSpaceReference addrSpace, u32 offset, u16 value, nMDBG::tStatus2* s)
{
 if (s && s->isFatal()) return;
 addrSpace.write16(offset, u16(value));
}

//=========================

inline void tSTC::tReg16IOWindowed16::write( tBusSpaceReference addrSpace, u32 offset, u16 value, nMDBG::tStatus2* s)
{
 if (s && s->isFatal()) return;
 addrSpace.write16(kAddressOffset, offset );
 addrSpace.write16(kDataOffset, value );
}

Any idea?

Thanks again

Best regards,

George

[DiegoF]

Hi George,

It's the hardware that determines what the addresses mean.  When accessing a windowed register the STC decodes the address written to the address register in terms of 16-bit words.  For the direct acccess a different hardware interface is used and addresses are in bytes.

I don't know if a different hardware implementation could give you 16-bit addresses for direct mode.  But the current implementation of STC devices use 8-bit addresses for the direct accessed registers.

Diego