What are the 3-bit field choices for Hw_Arm_Sel in PCI-6601

[JoeFriedchicken]

Hi Mark,

Yes, it is possible to trigger using an internal source. The feature is implemented from software: by strobing a register, you can assert one (or more) of the trigger lines.

Trigger_Drive :: Offset 0x600

Trigger_Drive is only 8 bits wide, and maps as follows:
7..0: The value of each bit is 'OR'ed with its associated internal trigger output.

So if you write 0b00000001 to Trigger_Drive, then internal trigger zero will assert and, if configured for positive edge detection, it will propagate through to whichever counters have been configured to arm-start on internal trigger zero.

[HortonMA]

Thanks Joe,

We'll try this and let you know how it turns out.

I have another question/problem.  While we were waiting on your response, we set up 3 clocks to each generate continuous pulse streams.  We used an external

trigger to start them.  We need these 3 signals to be in sync and they are not.  Basically, we disamed the three counters, set each up to generate a continuous pulse stream, armed the counters, and started them simultaneously witha gate.  We are using a 6602 and our source for all three counters is the 80MHz clock.  We examined the signals closely. It appears that when a TC is reached, there is a small amount of time added to our signals.  It varies between a half and a full clock tick of the 80MHz clock (12.5/2 to 12.5 nanoseconds).  As a result, our three signals are not in sync.  What do we need to do to get our three signals in sync?

Thanks Joe,

Mark Horton

[HortonMA]

Joe,

We fixed the syncing problem.  The small amout of extra time afetr each TC was a result of my load counts being off by one (one too big).

Sorry for bothering you with this one.

Thanks,

Mark Horton

[JoeFriedchicken]

No worries, Mark. I'm happy to hear you're over the hurdle 🙂

[HortonMA]

Joe,

Out inital efforts at trying this have failed.  Would you please elaborate on how one configures "for positive edge detection" and how to configure a

counter "to arm-start on internal trigger zero"?  I sure would appreciate the help.

Thanks in advance Joe,

Mark Horton

[JRWaldon]

To elaborate on Mark's post, we are trying to set up 3 clocks to start at the exact same time.  We currently have this working, but we are triggering the 3 clocks on PFI38, which is receiving a single pulse from the output of counter 7.  We would like to use an internal signal to start the 3 clocks to eliminate the external wiring and free up counter 7.

The changes we made are as follows:

set HW_Arm_Select to 0 in the counting mode register of each counter to select internal trigger zero

set HW_Arm_Enable to 1 in the counting mode register of each counter

write 0x01 to address 0x600 to assert internal trigger zero

This does not seem to work, as the counters never start.  I read in another post that we may need to set arm start trigger type to digital edge, but could not find any information on how to do that.

[Kirco]

Hi, I am unfortunately not at the moment in the office and can not access the code, but will be on monday. Then I will post the algorithm code we use to HW_arm the counter from the ext trigger. It should be more or less compatible with maybe small changes if you use internal trigger. Can you just for now try to set the following bit:

Write_G0_Command_Register_Arm(true);   (attention, this is not part of the DDK)

where G0 is the counter(s) you want to start. We also could not start the hardware triggered counter untill enabling this bit. It is more or less as software arm, but if you properly set the other bits it will arm from HW trigger (independant on external or internal signal)

Hope this helps, I will be back with more details on monday when I get in the office.

Kirco

[HortonMA]

Thanks Kirco,

If it is not part of the DDK, then I likely don't know the register offset.  I look forward to your post on Monday.

Thank Again,

Mark Horton

[HortonMA]

Kirco or Joe,

HELP!

Thanks,

Mark Horton

[JoeFriedchicken]

Howdy folks 🙂

I believe when Kirco said that "Write_G0_Command_Register_Arm(true)" was not part of the DDK, he meant that a function of that exact name wasn't part of the DDK's TIO chip object. Indeed, that register is documented (see [1], beginning on PDF page 53, or Chapter 3 page 13) and implemented (beginning on line 251 of tTIO.h).

I double-checked my last post, and I found a mistake 😕 I correctly gave the address for the Trigger_Drive register, but gave the wrong bit field offsets.

Trigger_Drive :: Offset 0x600

Trigger_Drive is 32 bits wide, and maps as follows:
31..24: TrigDrive
23..0:  0

TrigDrive provides a way to assert internal trigger lines from software. The value of each bit is 'OR'ed with its associated internal trigger output: bit 31 maps to internal trigger line 7, bit 30 to internal trigger 6, and so on...

[1] NI 660X Register-Level Programmer Manual

http://digital.ni.com/manuals.nsf/websearch/4CE1C778F442B01386256C870060F9F3