A couple of things. First, you can't drive the sample clock of the 4472 across the star trigger line. The only signal you can drive on the star trigger line with the 4472 is the sample clock timebase. On the 4472, the sample clock timebase either runs at 128 fs (51.2 kS/s < fs < 102.4 kS/s) or 256 fs (1 kS/s < fs < 51.2 kS/s). If you share this signal with the 7833, you will need to divide it down by 128 or 256 to match the sampling rate of the 4472. Your other option is to share the sample clock, but to share it through a PXI trigger line and not the star trigger line.
However, this still doesn't deal with the filter delay, which was your original question. For now, I'm assuming you have low-frequency alias rejection disabled. If not, things are more complicated and I don't want to add confusion for something you may not be using. If you don't know what low-frequency alias reject is, you're probably not using it since the default in the driver is to disable it. With low-frequency alias rejection disabled, the ADC filter delay is 38.7 samples. Depending on how tight of synchronization you need and how much work you want to do, there are a couple of methods you could try. The easiest approach is just to realign the data in software. Throw away the first 38 or 39 samples from the 4472 and this should should synchronize you to within .7 or .3 samples. By using an analog trigger on the 4472, you can also remove the integer portion of the delay since the trigger is generated from data that has already passed through the filter. You could also achieve this same level of synchronization by delaying the sample clock within the 7833 by N number of samples. Both of these methods would eliminate the need to realign the data in software. The tightest synchronization would be achieved by sharing the sample clock timebase from the 4472 and delaying the sample clock on the 7833 that is derived from it by N number of timebase ticks to compensate for both the integer and fractional delay. I haven't done a lot of LabVIEW FPGA programming, so I admit I don't know how practical the approach of dividing down the sample clock timebase within the FPGA is. The frequency range of the timebase is a bit weird and can vary from 256 kHz to ~13.1 MHz, but on paper it seems possible.
Hopefully this will give you some ideas of where you can start. Good luck!
