digital data regeneration with retrigerring

[Abhinav T]

Nir,

Can you post a screenshot of the rest of your code? It is difficult to debug this without knowing more details of your settings.

Abhinav T
Applications Engineer
National Instruments

[nirtzi1]

Hi,

Now we have a new problem.

We want to generate a new clk which is based on the same trigger (DMCS rate of 17Hz).

The new clk will be divided into frames, each frame has 48 risings rate of 4.2 MHz.

Between the frames we have 2 risings off.

At last we have clk which is divided into 50 risings: 48 active risings 2 not active.

Example is attached.

Best regards

Nir Berkocivh

[Abhinav T]

Nir,

I have attached some code that does something similar to what you want.

Abhinav

[nirtzi1]

Hi bhatinda,

I checked your example and it is not generate clock as I asked, please read again my specifications.

some details:

1. my trigger is 17Hz

2. my clock rate is 4.2MHz

3. the clock length is 14ms out of 56ms.

4. the clock is divided into frames of 50: 48 risings and 2 risings off.

example is attached.

thank you

Nir

[nirtzi1]

Hi again,

we are able to generate a clock as i described befor by using new trigger (tx frame sync rate 84k)

so the size of this clock is 48 risings but the problem is that my data's length is 59856 bits so it is not work properly.

how can i solve this problem???

thanks

if there is any way to contact with you through the phone it will be better.

Nir

[Abhinav T]

Nir,

It seems like you were working on this issue on a similar discussion forum post. I have taken that code and made it so that the data that code outputs is the data you are looking for. If you want to contact National Instruments you can go here to fill out a service request.

Abhinav