FPGA Digital Filter Design and Test using DFD Toolkit

[Sev_K]

Overview

This example demonstrates how to design a digital filter on the host (Windows) computer, convert the floating point filter design to a fixed point design and test the performance of the fixed point filter design on the FPGA (in simulation mode)

Description

This example shows how to create and test a lowpass IIR filter for removing high frequency components of a noisy signal. The LabVIEW project contains the following three main VIs:

1. Fixed Point Filter Design (Host).vi is used to design the digital filter, analyse the performance of the filter and generate fixed point FPGA implementation of the filter.

2. Fixed Point Filter Test (Host).vi is used to generate a test signal, send it to the FPGA VI for processing and then display the processed (filtered) data.

3. Filter Test Bench.vi is a VI under the FPGA target. It is responsible for reading the simulated signal from the host applying the filter (that was generated by Fixed Point Filter Design (Host).vi) and passing the filtered data back to the host.

Steps to Implement or Execute Code

1. Open IIRLowpass.lvproj
2. Run Fixed Point Filter Test (Host).vi
3. You can modify the behavior of the filter by making the necessary changes to the Fixed Point Filter Design (Host).vi , generating the new FPGA implementation of the filter and replacing the existing filter (in the Filter Test Bench.vi) with the new version of the filter.

Requirements

Software

- LabVIEW 2013

Hardware

- None