Use 'Edge Detection with Decimation' to created a task scheduler on your FPGA
Use 'Edge Detection with Decimation' in the 'Clock Management' time-loop to generated synchronized events on your FPGA. For each task that you wish to have execture off of one of these signals, create another loop with a nested case structure. Place of the task code in the true case. Clock events from the Clock Management or an asynchronous reset will cause execution of the task. You could also add other triggers for each task including hardware inputs, user events, etc.
