FPGA Timing and Triggering Reference Architecture

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Description

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Introduction

Many CompactRIO applications require precise triggering over a set duration. As an example, consider a soda dispenser. When a consumer places a soda cup beneath the dispenser and engages the trigger, soda is dispensed until the consumer disengages the trigger. If it is an automatic soda dispenser, soda is dispensed for a set duration specified by chosen the cup size. Now consider the case where the automatic soda dispenser is dispensing soda across an array of soda bottles as a part of an assembly line. How can we utilize FPGA timing and triggering to solve this problem?

Reference Architecture

The Timing and Triggering Reference Architecture utilizes encoder positions to trigger a digital output line. The digital output goes high for a set duration described in terms of FPGA clock ticks as shown in Figure 1.

Figure 1. Timing and Triggering Lines

The architecutre is implemented using a Master-Slave architecture. The FPGA Master is responsible for receiving position and duration information from real-time through DMA FIFOs and placed in dedicated memory spaces. Once all the position and duration information is received for the current pass, the FPGA Master sets an occurrence to begin execution of the FPGA Digital Output Slave. Once the FPGA DO Slave receives the occurrence, it then reads from the duration and position memories. If the duration is not zero, it checks the current encoder position to determine if the trigger encoder position has been reached. If the trigger encoder position has been reached, the digital output trigger is turned on and continues to stay on until the duration is complete. Further details can be found in Figure 2.

Figure 2. FPGA Timing and Triggering Architecture

It is important to note that each position and duration in memory corresponds a single FPGA DO Slave at a single trigger encoder position. As a result the size of the position and memory blocks are X x Y where X is the number of FPGA DO Slaves and Y is the number of trigger encoder positions for a single pass in either the positive or negative directions. The real-time portion of the code is responsible for setting the direction of the move prior to execution. This is set after receiving and IRQ generated by the FPGA Master.

Communication mechanisms between the real-time, FPGA Master, and FPGA DO Slave codes are described in Figure 3.

Figure 3. FPGA Timing and Triggering Communication

Example Code

Example code using the FPGA Timing and Triggering Reference Architecture is attached. In order to open and view it successfully, LabVIEW, LabVIEW RT, LabVIEW FPGA, and the LabVIEW Simple Messaging Reference Library is needed. Please post any comments or feedback as it is greatly appreciated.

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