Hysteresis Trigger Example and IP Core for LabVIEW FPGA

[J Ho]

Overview

This code demonstrates how to implement a hysteresis trigger in LabVIEW FPGA.

Description

This example uses basic logic functions, simple comparisons and a small state machine to implement a hysteresis trigger in LabVIEW FPGA.

The example implements a two-channel, configurable hysteresis trigger with the option to implement a logic combination trigger (i.e. if trigger 1 and trigger 2 are true, then combo trigger true). The example makes use of the hysteresis trigger IP core which receives the trigger configuration and the channel data, and then outputs a boolean signal if the trigger conditions are true. The example can be easily extended to work with more than two input channels as trigger source.

This example will not work within a Single-Cycle Timed Loop (SCTL), as it monitors an analog input channel as the input to the hysteresis trigger. IO-Nodes for analog input channels are not available within SCTL for most of the available FPGA hardware targets.

Single-Cycle Timed Loop FAQ for the LabVIEW FPGA Module - National Instruments
http://digital.ni.com/public.nsf/allkb/722A9451AE4E23A586257212007DC5FD

Requirements

 Software

• LabVIEW Base Development System 2012 (or compatible)
• LabVIEW FPGA Module 2012 (or compatible)

 Hardware

• No hardware is necessary to use this example VI

 Steps to Implement or Execute Code

1. Download and open the attached ZIP-file
2. Open the [Main]...VI and follow the instructions inside

Additional Information or References

**The code for this example has been edited to meet the new Community Example Style Guidelines. The edited copy is marked with the text ‘NIVerified’. Read here for more information about the new Example Guidelines and Community Platform.**

[mtitoo]

Great work! Just had to change default state of feedback loop init to Armed so that if initially the input value exceeds the limit it triggers the output