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IRIG106 Chapter 10 Stream - cRIO Sample Project

by:
‎09-02-2020 09:35 PM
Last Edited by: telles_s ‎09-03-2020 01:19 PM

Products and Environment

This section reflects the products and operating system used to create the example.

To download NI software, including the products shown below, visit ni.com/downloads.

    Hardware

  • CompactRIO|SingleBoardRIO

    Software

  • LabVIEW
  • LabVIEW FPGA Module
  • LabVIEW Real-Time Module

Code and Documents

Attachment

Description

It is a implementation of IRIG106 Chapter 10 UDP stream accordingly with the following documentation:

Ref1: IRIG 106-07 CHAPTER 10 PROGRAMMING HANDBOOK

Ref2: CHAPTER 10 Digital Recording Standard

Ref3: CHAPTER 11 Recorder Data Packet Format Standard

 

Overall Packet Structure (Ref3 page 10)

 

 

There are a variety of data types supported (check Ref3 page 14). In this sample project was implemented Analog Data Format 1 (packet header value = 0x21), segmented and non-segmented stream, and Time Data Format 1 (packet header value = 0x11).

 

Analog Packet Non Segmented Module

Dequeue data from the channel data fifo, encode and enqueue in the data packet queue.

 

Analog Packet Segmented Module

Dequeue data from the channel data fifo, segment, encode and enqueue in the data packet queue.

 

Time Packet Module

Dequeue timestamp value from its fifo, encode and enqueue in the time packet queue.

 

These packets require a Real Time Counter for the time packet and a Relative Time Counter (48bits 10MHz) for every packet header (check Ref3 page 17).

 

Relative Time Counter Module

Associate 2 cRIO counters for the 48Bits RelativeTC and allocate a 3rd counter as 1ms pulse generator exported to cRIO Trigger Line 5 to sample the 48Bits RelativeTC and the Real Time Counter. Enqueue RelativeTC values according with the packets time required.

 

Real Time Counter Module

Sample cRIO timestamp in FPGA (every cRIO Trigger Line 5 pulse) for minimum Jitter and enqueue in the RealTC fifo.

 

First packet to stream must be the Time Packet (Ref2 page31) and a minimum frequency of 1Hz. The udp time packet not necessarily every exactly 1Hz because UDP is not deterministic, but the Relative and Real TC values should be precise corresponding 1 second increments, for example the RelativeTC (48bits 10MHz) value: 0, 10000000, 20000000, 30000000, etc.

 

Thus, before stream all UDP packets a UDP sequencer was created to sequence all packets accordingly.

 

UDP Module

UDP sequencer engine prioritizes time packets and ensures that segmented packets are not interrupted by another packet.

UDP engine stream all packets thru UDP multicast mode.

 

Included in the Sample Project are:

  • I106_Chap10_Stream-Simulated.vi : Simulate 2x 50kS/s channels as segmented analog data and 2x 100S/s as non-segmented analog data. Both are ramp waves, for easy debug in the server side or network protocol analyzer tools (e.g. Wireshark);
  • I106_Chap10_Stream-9215.vi : Acquires data of 2x 9215 using the same I106 Chap10 configuration as simulated;
  • Chap10_UDP_Receiver.vi : Host VI to listen a specific UDP multicast port;
  • Chap10_UDP_Receiver-TimePacket_Decode.vi : Host VI to listen time packet UDP port and decode time packets.

 

OBS: notice that packets header nomenclature follows the Ref1 document.

 

 

How to Use

  • Change the IPs for you setup;
  • Select Sample Mode;
  • Run the cRIO VI;
  • Run Host VIs to monitor.

 

Additional Information

  • cRIO|sbRIO that supports DAQmx;
  • CompactRIO driver >= 18.5
  • Attached LabVIEW project = 2018

 

Example code from the Example Code Exchange in the NI Community is licensed with the MIT license.

Contributors