Overview
This project contains an FPGA VI that comprises of several counters for several digital lines that also provides the time in order to calculate frequency.
Description
The FPGA Counter.vi contains the code for calculating the events occuring and the counter logic (encased in the SubVI "Counter logic.vi) as well as the time over which those events occured and then sends them via a front panel control up to the RT vi.
In the RT VI, the number of events are then divided by the time taken in order to give the RPM.
Steps to Implement or Execute Code
- Open Project
- Make sure appropriate harware is in the Project and connected - move to another project with appropriate harware if neccessary.
- Compile and run
Requirements
Software
LabVIEW 2013
Hardware
Any NI RT and FPGA hardware with digital IO - cRIO or FlexRIO for example
Additional Images or Video
Liam A.
National Instruments
Applications Engineer
