cRIO Reference Trigger on FPGA with Data Streaming to Real-Time

[James_McN]

Overview

This example demonstrates how to implement a reference trigger on FPGA and stream trigger data to Real-Time application.

Description

Implementing reference trigger on FPGA typically requires memory on the FPGA for all your samples. This limits the number of samples that you can acquire using this method. This code only requires enough memory for the pre-trigger samples and when the trigger fires it streams the pre-trigger samples and then the post-trigger samples from a circular buffer thus allowing much greater sample sizes.

Requirements

 Software

• LabVIEW Full or Professional Development System 2012 (or compatible)
• LabVIEW Real-Time Module 2012 (or compatible)
• LabVIEW FPGA Module 2012 (or compatible)

 Hardware

• Compact RIO FPGA and Real-Time target (e.g. cRIO 9024 or compatible)
• Analog Input C Series Module (e.g. NI 9215 or compatible)

Steps to Implement or Execute Code

1. Download and extract the attached file "Reference Trigger on cRIO LV2012 NIVerified.zip".
2. Follow the instructions in Real-Time and FPGA Front Panel and Block Diagram and run the program.

Additional Information or References

FPGA VI:

Write data into a circular buffer with a subVI generating the write addresses. When the trigger fires the subVI also generates the address for the oldest item in the buffer. Once all the requested samples have been written to the FIFO the FPGA flags to the RT and stops executing. To make this retriggerable simply loop!

We are generating the trigger from RT for testing but this could come from analog values on the channels or another part of the FPGA code.

Real-Time VI:

On the RT side we just have to wait for samples to be available and keep reading them until the flag is set to complete the samples:

**The code for this example has been edited to meet the new Community Example Style Guidelines. The edited copy is marked with the text ‘NIVerified’. Read here for more information about the new Example Guidelines and Community Platform.**

[RonnyVel]

Hi James

I am trying to develop this myself but I dont know where to start. I dont like the idea of buffering into block memory as i dont want to limit the amount of post-trigger values from the FPGA to the host. I would rather set a predefined pre-trigger buffer length (say 5000 samples) and stream that to the host along with post-trigger samples.

I see that there is a bug in the first screen shot, i.e. the image is not showing the FPGA implementation. are you able to email me the details if you dont mind.

my email address is ronny.veljanovski@live.com.au

Looking forward to your reply.

Ronny

[RonnyVel]

Hi James

Thanks for the quick response. The concept is very streamlined and cool.

I will work on it tomorrow and see if it works once I make some changes to my VI's.

Thanks again

Ronny

From: JamesMcN <web.community@ni.com<mailto:web.community@ni.com>>

Reply-To: "ni-2144636708-170q-2u-bm4@decibel.ni.com<mailto:ni-2144636708-170q-2u-bm4@decibel.ni.com>" <ni-2144636708-170q-2u-bm4@decibel.ni.com<mailto:ni-2144636708-170q-2u-bm4@decibel.ni.com>>

Date: Thu, 10 Mar 2011 21:07:27 +1100

To: Ronny <ronny.veljanovski@crcbid.com.au<mailto:ronny.veljanovski@crcbid.com.au>>

Subject: - Reference Triggers on FPGA (With Data Streaming)

Community<http://decibel.ni.com/content/index.jspa>

Reference Triggers on FPGA (With Data Streaming)

modified by JamesMcN<http://decibel.ni.com/content/people/JamesMcN> in NI Developer Community - View the full document<http://decibel.ni.com/content/docs/DOC-15052

[htarlek]

Hi,

I was wondering why you had decided to use a separate block memory for each Analog Input.   Is it possible to have one block memory and interleaved data from each into this?    Thanks!