Examples and IP for Software-Designed Instruments and NI FlexRIO
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NI Instruction Sequencer IP »
This IP contains a memory to hold sets of instructions, called sequences, which can be issued from the IP on the FPGA to another component on the FPGA, such as a digital protocol generator. This facilitates FPGA-based reconfiguration.
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Description: This IP contains a memory to hold sets of U32 data values, or instructions. Instructions are grouped into sequences, and there may be one or more sequences in the memory. Events on the FPGA cause an entire sequence of instructions to be sent to the downstream IP, accommodating back-pressure or flow control. After a sequence is generated, the IP advances to the next sequence in the memory. Once all sequences have been generated, the IP returns to the first sequence, enabling looping.
Additional Documentation:
- After Installation - C:\Program Files (x86)\National Instruments\LabVIEW 2012\user.lib\_NI Instruction Sequencer IP\documentation\NI Instruction Sequencer IP.pdf
Compatibility:
- LabVIEW Versions: 2012
- LabVIEW FPGA Module: 2012
- Verified hardware targets: NI PXIe-5644R, NI PXIe-5645R
- Links to relevant examples: NI Instruction Sequencer and SPI Example for the NI PXIe-5644-45R
Dependencies:
- none
Performance:
- Clock rates up to 180 MHz
- Up to 32-bit instruction word lengths
FPGA Footprint:
Xilinx Virtex-6 LX195T:
- 0.3% / 352 LUTs
- 0.2% / 401 Flip-Flops
- 0.2% / 1 Block RAMs
- 0.0% / 0 DSP Slices
- 180 MHz maximum achievable clock rate (empty FPGA)
Latest Version:
Previous Versions:
- none available
Note: All source on this community is distributed using VI Package Manager (VIPM). For more details on VIPM, please read A Note on VI Package Manager
