Stream Controller IP

[Example_and_IP_Admin]

Stream Controller IP » This IP controls the writing and reading of data to and from FIFOs on the FPGA.

Description: Some applications require offloading the data from the FPGA in the VST to another device. This can be accomplished in several ways: DMA FIFOs to a host system, Peer-to-Peer DMA FIFOs to other devices in a PXIe system, or through the front-panel DIO of the VST. Or, some applications require transferring data to another clock domain for processing, which can be done using local FIFOs. This IP provides an API to control the reading and writing of the FIFOs used in these applications.

Additional Documentation:

• After Installation - C:\Program Files (x86)\National Instruments\LabVIEW 2012\user.lib\_NI Streaming Controller\documentation\Stream Controller.pdf

Compatibility:

• LabVIEW Versions: 2012
• Verified hardware targets: NI PXIe-5644R
• Links to relevant examples: Streaming Host Example for the NI PXIe-5644R

Dependencies:

• NI Basic Elements IP

Performance:

• 1 input I/Q pair per loop iteration / clock cycle
• <±,18,1> fixed point
• 1 channel on output stream
• 2-wire handshaking

FPGA Footprint:

Xilinx Virtex-6 LX195T:

• 8.5% / 10628 LUTs
• 5.2% / 12956 Flip-Flops
• 4.1% / 14 Block RAMs
• 0.0% / 0 DSP Slices
• 140 MHz maximum achievable clock rate (empty FPGA)

Latest Version:

• Stream Controller  IP 1.0.0.2 (LabVIEW 2012)

Previous Versions:

• none available

Note: All source on this community is distributed using VI Package Manager (VIPM). For more details on VIPM, please read A Note on VI Package Manager