Hi Adnan,
I had the FPGA VI along with the whole project compiled in another PC for testing and then finally moved it on the intended target.(Same configuration). Like I had mentioned, everything was working fine until I had to recompile the VI due to changes. Since then, I started receiving the mentioned error. I had already check the
properties and the
RIO0::INSTR was already there.
In another thread, someone else was receiving the other related error code and he mentioned to disable
automatic close VISA settings. I did the same in the Project RT Target and within the labview options. Rebooted the PC and PXI chassis and the RIO device was accessible.
I clicked on reset and no error dialog boxes either.To be curious, I reenabled the
automatic close VISA settings and it still works normal.

I never realized how significant this checkbox turned out to be in this version .

Thanks,
Ashm01