Operazioni parallele

[Rob_F]

Ciao a tutti,

premetto che non sono proprio un esperto di Labview e al momento ho un problema che non riesco a risolvere.

Con un CRIO devo acquisire dei segnali analogici provenienti da accelerometri a 5000 Hz con un modulo NI 9233 e 13 segnali digitali provenienti da un encoder assoluto a 100000 Hz con un modulo NI 9401per determinare posizione e velocità. Ho provato a far girare queste due operazioni  parallelamente sull' FPGA e ho letto i dati dalla VI sul real time semplicemente leggendo gli indicatori dell'FPGA. In questo modo però i dati vengono letti con dei secondi di ritardo! Credo di stare sbagliando il modo in cui i dati vengono trasferiti dall'FPGA al Real-time ma davvero non riesco a trovare la soluzione. Per chiarire meglio il problema ho allegato due VI, una per gli accelerometri e una per l'encoder. Prese singolarmente queste due Vi funzionano a dovere ma quando cerco di eseguirle parallelamente sull' FPGA ecco che nascono problemi.

Qualcuno potrebbe spiegarmi come eseguire parallelamente le due operazioni e leggere i dati dal real-time ad un'alta velocità?

Grazie davvero a tutti !!!

[JMota]

Ciao Rob,

Io non parlo italiano, ma he notato cosa male nel vostro VI.  Io parlo espagnolo ed inglese, e continuero in inglese. (I apologize for any improper use of Italian)

Didn't fully understand your problem, but looked at your VI and I suggest you look to the new VIs I'm attaching and the following example "examples\CompactRIO\Module Specific\NI 923x\Synchronizing NI 923x Modules"

Hope this helps. Buona fortuna.

JMota
National Instruments

[Rob_F]

Ciao JMota,

thanks for the answer but I think I incorrectly exposed my problem. I need to acquire data from both accelerometers and encoder and I think I can do it in the same FPGA VI with two different while loops with their own loop timers. I attached the FPGA VI to make thinks clearer. It works but with a long delay in the data acquisition for the encoder i.e. if i turn the shaft of the encoder manually, i can read the position and the speed of the shaft on the front panel only 1-1.5 seconds after. No problems att all with acccelerometers.

I attached also the real-time VI I used for this application; could you please give it a look and suggest me how to change it and make everything faster?

Ciao and thousand thanks!

Rob_F

[JMota]

Hi Rob_F,

I took a quick look to your VIs and I'm not sure why you are seeing that 1-1.5 seconds delay. I think the problem lies on the way you are communicating data from the FPGA to the Host VI and possibly in the way your host VI is structured. I have some questions and suggestions.

- What hardware are you using?
- What is the loop rate for your host VI?
- What is the value of the "Total Period" indicator on the FPGA VI?
- If you run the FPGA VI in interactive mode, do you see the position information being updated properly?
- I suggest you transfer the encoder info back to the host as one integer instead of a cluster. That will make the data transfer more efficient.
- Just as an experiment, simplify your Host VI to only acquire data from the encoder as in the attached VI. Do you get more frequent updates?

Please post back the answers to the questions and any new findings. If you can post the LV project and the bitfile you are using that may help too.

Regarding the usage of the 9233 modules, if you want the data you get back from both modules be synchronized (which I suggest you do unless you have a good reason for not doing it), you must get them share the same timebase (refer to the synchronizing 9233 modules topic in the documentation), then put both Start channels in a single node, and all the Analog Inputs in one node inside the while loop.

If you ever need to acquire data from the 9233 modules at different rates, your FPGA VI will not work as it is now. For information on how to implement that, refer to the "Acquiring Data from Synchronized NI 923x Modules with Different Data Rates" section in the "Synchronizing Multiple NI 923x Modules" topic in the LV Help.

JMota

[Rob_F]

Hi JMota!

Some updates:

I'm using a CompactRIO 9104 with two NI 9401 and two NI 9233 modules, the software is Labview 8.0.

After some readings on the subject I decided that, for the amount of data I need to transfer to the host on RT, it was better to use DMA FIFOs. Talking only about the encoder part,as I wrote before the while loop on the FPGA is running at 100kHz and every time i store in the DMA FIFO two elements: the first which( with some operations on it afterwards) will give me the position of the encoder, the second that will give me the speed of the shaft of the encoder. I set up the FIFO depth at 8191 elements: I thought that if I write two elements in the FIFO at 100 kHz I will have to read from the FIFO on the RT 200 elements each 1 ms ( I'm using a timed loop which goes up to maximum 1kHz). This doesn't work. I placed an indicator which tells me the number of elements remaining in the FIFO and it never goes to zero even if I tell the FIFO.read to read 202 elements every 1 ms. In order to understand this problem I decided to change the acquisition rate to 1ms so my DMA FIFO would have to be full in about 4 seconds and this actually happened the first time I run only the FPGA VI after compiling it. The problem is that if I run the VI again the full flag immediately switches on so it means that every time the FPGA runs the FIFO write method finds the FIFO memory full, am I right? What happens then if I try to read the data from the host through the FIFO read method? I guess that even in this case the FIFO.read will find the memory full. Any suggestions to solve this problem? I've attached the FPGA and RT VIs so you can immediately see if I'm doing things right

I thank you once again!

Ciao

Rob_F

[JMota]

Hi Rob_F,

Tranferring data to the RT application (the host) through DMA is the most efficient way to do so, unfortunately it is a little bit harder to use than regular controls and indicators. Overall I think you are in the right track. I have some answers and suggestions for you.

The reason why it took 4 seconds to get the full flag the first time, and it was immediate the subsequent times is because by solely running the FPGA VI you are not clearing the FIFO; first time it ran the FIFO was empty and it got full, subsequent runs the FIFO was full. To prevent this from happening, I suggest you keep the Open FPGA Reference configured for Open (instead of Open and Run), then execute the Reset invoke method right after the Open, followed by the Run invoke method. This will ensure that your DMA FIFO will be clear once your FPGA VI starts running. Also, I don't think you need to use the FIFO.Configure and FIFO.Start nodes for your application. They are useful when you need to have very fine control over the communication, which I don't think you need for you application (I would suggest to not use them unless you find a good reason for using them). If you haven't checked the FPGA DMA examples, I suggest you take a look to them (LabVIEW 8.2\examples\FPGA\CompactRIO\FPGA Fundamentals\DMA).

Given your VIs, it is normal that the Read FIFO host method will tell you that there are still some elements left in the FIFO, since the Host and the FPGA VIs run concurrently with different clocks, and you have your FPGA VI continuously writing data to the FIFO. What you probably want is to make sure the FPGA VI does not overfill the FIFO by having the Host VI read from the FIFO at a higher rate than the FPGA is writing to it.

By the way, I found this discussion that you may find useful. It contains some example code of using DMA to acquire data from a 9233 module.

http://forums.ni.com/ni/board/message?board.id=280&message.id=1458&requireLogin=False

Hope it helps.

JMota

[Rob_F]

Thanks a lot JMota,

your explanations have been very helpful!

Have a nice day!

Rob_F