Hi:
I'm very happy to learn NI introduced HMB as additional memory for FPGA, I myself did some test, and I have some question about it.
I learned from the Best Practices in "NIWeekHMBFinal", that to get best performance, we should constantly request memory data so that we will get max out of this interface, but I noticed if i issue data request @40MHz, I will have some missing data, the retrieve data node will give Output Valid false from time to time, the ration might be 1~5% compares to the total request I made.
I simply modified the "Additional FPGA memory" example to make the test. and made sure "Write Data" and "Read Data" is always true, then I add counter at the "Output Valid" to see how many time it gives invalid output.
In my imagination, I hoped there were only be fix amount of invalid data from "Retrieve Data" at the start of operation, and as everything runs to stable state, there shouldn't be any more invalid data came out from the "Retrieve Data". But that not the case, it will give out invalid output every once in a while. And during the test I wasn't running anything at the RT core.
Will there be a better way to use HBM as pure FPGA memory? 40MHz is good enough for my application, but I wish I can avoid data missing.
My application need me to read a data from memory and write back to the same address when I finish certain operate to that data, and do the same thing to next memory address. I'm doing it purely sequential, so the latency in read wouldn't be such a big problem, but I do hope that I can do this operation contiguously，any advice?
