Serial communication in FPGA

[PiDi]

Hello

Is it possible to use the RS232 Serial Port defined in CLIP directly on FPGA?

Context:

We're upgrading application from sbRIO 9606 to SOM. We're currently using our own implementation of RS232 on FPGA. I would be nice if I could get rid of this RS232 code and just use native RS232 on SOM.

Here's "the picture worth a 1000 words" of what I'm trying to archieve:

[KHartley]

Hey PiDi,

Our 9870 module does have a fpga personality. We do not have a c series module support on the SOM (sbRIO-9651).

The clip serial ports are connected to a driver in RT, unfortunately this is the functionality you are not asking for.

Would you mind private messaging me your email and contact info we may be able to discuss some other options available?

[nturley]

Technically it is possible but I doubt it's worth the trouble. Interfacing with a component like that would mean interfacing with it's bus interface. This UART component uses the regport interface, and we haven't published how it works.

If you are really serious about not maintaining this code, I suspect that there are other UART implementations out in the wild that expose a more friendly interface. It would probably be less work to get one of those working.

[PiDi]

Kyle,

you have a new message

nturley,

it's not really big trouble for me to maintain this code (it works fine). I'm just wondering if I could get rid of some code in the upgrade-and-refactor process. So, hacking undocumented interfaces sounds like a ton of problems, and switching to other in-code implementation probably doesn't give any value.

[MrJackHamilton]

PiDi,

I don't see why you cannot do this. If you have existing FPGA LV code, you can port it over the to 9651. You WILL have to create the CLIP file to provide the I/O line configuration for the serial Rx & Tx lines.

I have done a 'roll-your-own' RS232 port on the SOM because I needed 3 serial interfaces.

It should work. I'm not sure you understand what a CLIP is, It's merely the low-level line configuration and assignment of the FPGA, it does not encompass 'FPGA' code in the sense of logic.

Regards

Jack Hamilton