Using Desktop Execution Node with sbRio-9651

[cbl-jnj]

When I attempt to use the Desktop Execution Node (DEN) with FPGA code written on a sbRIO-9651 target, the only available resource listed under the FPGA Target in the DEN configuration dialog is the Onboard I/O. I expected to see the I/O from the Socket, defined by the CLIP. Am I doing something wrong, or are my expectations incorrect?

Cheers,

Chris

[Call.Me.Wilbur]

Hi Chris,

You're not doing anything wrong, this is expected behavior. The socket I/O is not accessible in DEN under the FPGA's available resources. However, you should be able to access any controls or indicators that are wired to the I/O nodes you use in your VI.

Will

National Instruments

[cbl-jnj]

Hello Will,

Appreciate the reply, and I do see all the controls and indicators on the the front panel of our FPGA_Main.vi in the DEN.

I was hoping to do some timing studies of our FPGA code, but none of the I/O items are also wired to indicators. The main reason there are no indicators is that our fabric usage is high and we have reduced the number of controls and indicators in general.

Any suggestions on how to study the timing of I/O items used in the sbRIO-9651 with simulation?

[Call.Me.Wilbur]

Chris,

In that case, your best bet may be to try one of the third-party simulation options.

If you choose that route you might find this tutorial helpful:

Cycle-Accurate Simulation with Xilinx ISim

Also, compatibility of Mentor Graphics software will be dependent on your version of LabVIEW.

Will

National Instruments

[cbl-jnj]

Wow - this is going to be quite an amount of work.

<customer request>It would be very nice to have the socket IO available in the DEN</customer request> 

I've started working my way through the example, but there are no instructions regarding the access of IO items of the socket. In the file tb_NiFpgaSimulationModel.vhd there are examples for:

• This is an example of how to read an indicator
• This is an example of how to write a control
• This is an example of how to read a Target To Host DMA FIFO
• This is an example of how to write a Host to Target DMA FIFO
  

Can you help me determine how to add the IO item?

BTW, I'm a Windows LabVIEW user of 20+ years, but have no experience with Xilinx tools.

[cbl-jnj]

NVM, it looks like the IO is added automatically, I just ran RegenerateXSim.bat and see the IO. To be continued....

[cbl-jnj]

Couple things to note

• LabVIEW 2016
• Windows 10 (I know FPGA compile tools not supported but they work 🙂
• Following the instructions at Cycle-Accurate Simulation with Xilinx ISim,
  • I get the options of Questa Simulator or Xilinix Simulator. I selected Xilinix Simulator.
  • Launching simulator via RegenerateXSim.bat runs Vivado and I can run simulation, though the steps are different but similar to ISim

I was able see simulation:

simulation

for this simple fpga main code.

fpga code