How do I output signals properly from my FlexRIO to the 5781 DAC?

[mhsu]

Hi

I am having problems with a very simple task. Basically I have a 5781 module attached to a FlexRIO, and would like to output high frequency sine wave signals (> 1 MHz). 

The FlexRIO is running on a single cycle timed loop at an FPGA clock speed of 40 MHz. This is generating a sine wave signal, which is then passed to a FIFO (target scoped) input.

The FIFO output is now passed to another single cycle timed loop running on I/O clock 1 (DAC clock) at 40 MHz. This FIFO output is connected to the DAC output 0, within this separate loop.

For some reason when I do this, the DAC output (observed on an external oscilloscope) has nothing that resembles a decent sine wave, instead it flickers and jitters. I have checked that the sine wave generation is good, since it runs on the FPGA nicely. So somehow the use of the FIFO to pass data between two separate single cycle loops running on different clocks is corrupting my signal, or introducing timing jitter.

My questions are as follow:

1) Is the use of FIFO's the right thing to do to pass data between single cycle loops running on different clocks? Note that the clock rates are the same.

2) Do I need to somehow synchronise the DAC and FPGA clocks?

3) What is wrong with the logic of my code?

I would be glad if you could please provide some tips.

Cheers.

[PaulRB]

Hi,

To answer your questions:

1) Yes, the use of FIFOs to transfer data across clock domains is correct. However, if you are using the IO Mod Clock, the frequency is actually 100 MHz, as defined by the CLIP. Therefore, this could be causing some of the strange behavior that you are seeing.

2) No, you do not need to sync the DAC and FPGA clocks.

3) It is difficult to tell if your logic is correct without seeing the code. Could you post a screenshot? Also, what CLIP are you using? If you are using the System Synchronous CLIP, it does not have IO Module Clock 1 connected.

Here are some suggestions for debugging:

1) Fill up the FIFO in one loop and then stop writing to it when it is full. Then in the output loop, read from the FIFO. This will eliminate any timing issues.

2) Make sure you are monitoring the timeouts on both the FIFO reads and writes. This could give some insight into the strange behavior.

Please let me know if you need any more help.

Thanks,

[mhsu]

Thanks for the reply, Paul.

Please find attached a screenshot. I still have some questions:

1) Why can't I run the whole system at 40MHz (i.e. for both FPGA clock and I/O Module 1 clock)? After all, you can configure the I/O Module Clock 1 properties to compile between 10 and 100MHz. Are you saying that this configuration does not actually do anything to the clock and it will only operate at 100MHz? What does the configuration actually mean?

2) If I would like to synchronise the FPGA and IO Module clocks together, how do I do this?

3) I am not sure what the system synchronous CLIP is. Do you have a description for this?

I really appreciate your help in this.

Cheers,

Magnus

[PaulRB]

Hi Magnus,

The configuration settings will set some timing constraints in the VHDL and for the most part should be transparent to the user. The actual IO Module Clock will be running at 100 MHz.

You can use an external 40 MHz signal as a clock for your 5781. There are some examples that show how to set this up in the example finder. Specifically, the NI-5781 - Clock Select.lvproj should help.

The System Synchronous CLIP is just another option for your 5781 CLIP. You can click on it in the Module properties to see more information.

[mhsu]

Thanks for the tips Paul. More specifically, how do I synchronise the FPGA clock to the IO Module Clock?

[PaulRB]

Hi,

I know you can divide the IO module clock, but only by certain integer values. Thus, you won't be able to divide it down to the 40MHz which is required for the sine function to run. Do you want to be able to change the frequency? If not, you can generate one cycle of the sine wave in the 40MHz loop and then continually output this data in the 100MHz loop. 

[mhsu]

I tried running this program, to adjust the clock settings on the 5781.

I tried changing the Clock Select from 0 (PLL off) to 1 (PLL on) to 2 (External clock), however, I could not get the 5781 to do anything other than its default setting 0 (PLL off).

Do I need a PXIe-796xR to operate the PLL? My current hardware is a 5781 attached to a PXI-7954R.

[PaulRB]

Hi,

What is your ultimate goal with this project? If you only have one flexrio module, there should not really be any difference between PLL off and PLL on since you're not trying to phase lock multiple module clocks. However, if you are providing an external clock, you should be able to set the Clock Select to '2' to use that clock. Are you not seeing this?

If your goal is to just output a sine wave, you can set up the sine wave as an initial value in memory. In the memory properties, you can select 'Initial Values' and then chose the Mode to be 'Sine.' This will preload the memory with a sine wave that you can read over and over in your loop. Will this accomplish what you want? 

[mhsu]

Hi,

Thanks for the reply.

My ultimate goal with this project is to acquire 2 analog signals using the high-speed ADC, process these signals in the FPGA and then output 2 analog signals using the high-speed DAC. This whole program runs as a feedback control loop. I have implemented this program, however I notice that there is a fair amount of frequency/phase jitter on the DAC outputs, with respect to the ADC inputs.

The reason for this, after doing multiple tests, is I believe the non-synchronisation between the IO Module Clock 0 (the 5781 is operating in synchronous mode) and the FPGA clock. Both clocks are clocked at 100 MHz, but the IO Module Clock 0 is not phase locked to the FPGA clock - thus the phase jitter. If I can phase lock these two clocks, I am quite certain that these phase jitter issues will go away.

However, right now, I cannot seem to get the 5781 to lock to the IO Mod Sync Clock. Please see attached. Do you know why this bit is grayed out?

M

[PaulRB]

Hi,

The reason this is grayed out is because the IoModSyncClk is only available on 796x Flexrio modules. Is it possible to clock all of your FPGA code using the IO Module Clock? You won't be able to set it as your top level clock, but you should be able to clock your loops with it. 

Thanks,