How do you capture IQ data with RFSA vi's triggering from ext trg on digitizer?

[jltetzlaff]

I am trying to write an application using RFSA vis that will capture IQ data when triggered from the external trigger port on the digitizer card.  This does not seem to be supported by the RFSA vis and I am not sure how to integrate ni-Scope and niRFSA in one application.

[Paul_C.]

Hi jltetzlaff,

The easiest way for this to work would be to use the niRFSA Configure Digital Edge Start Trigger.vi.  This will allow you to select PFI0 or PFI1 which can be connected to through the 9-pin mini-circular DIN connector on the front of the digitizer.  Is this not acceptable?  If that won't work, I can look into ways to use that external trigger port.

Regards,
Paul C.

[jltetzlaff]

I am syncing my device under test with a 90 ms clock signal originating from an AWG.  This caused my DUT to transmit on the rising edge of this clock.  I want to set up the RFSA to capture data from each transmit pulse without having to use an IQ power edge trigger.  An alternative would be to have the AWT generate to 90 ms clock for me.  Is it posible to output a clock running that slow from the PFI0 or PFI1 ports?  The signal required is 90ms period, 1.5Vpp, 750mV offset, 47% duty cycle.

[Paul_C.]

Hi Jltetzlaff,

The Clk in and Clk out ports on the 5142 can be used to input and export a reference clock.  You can import this as your sample clock source over the Clk in by using a simple property node.  This is assuming your using LabVIEW.  My main concern is regarding your clock.  If you take a look at page 20 of the reference manual here: http://www.ni.com/pdf/manuals/374300c.pdf, you can see the PFI lines follow a very specific digital logic specification (TTL).  It looks like your signal won't be recognized properly by these lines.  The lines require a voltage above 2.0V to register high.  There is no minimum frequency on these PFI lines.  The problem is the logic levels.  My recommendation would be to export a start trigger with your AWG to begin the RFSA session.  If I'm misunderstanding the setup, could you please give more details on devices (model numbers), development enviroment (LabVIEW etc.), and what connections you require.  From what I understand, you want to sync the RFSA devices with the AWG and DUT.  Perhaps the session from the AWG that is generating the clock can also export an event to start the AWG to start the RFSA device through PFI 0 or PFI 1.  This can be done using the niFGEN Export Signals.vi.  The exported signals by this vi will follow the correct logic accepted by the 5142 digitizer in the RFSA setup.

I hope this helps,
Paul C.