High-Speed Digitizers
Trigger Edge Configuration for PXI 5124. Visual C++ Design.
Hi Piju,
I wanted to apologize, it seems I misread your post. From what I'm seeing in your trigger representation, there is really no need to setup two triggers. This is only true if the start trigger goes high at the same time as the acquisition trigger and never goes back to a low state. If this is true, then you only need to set up the reference trigger.
Setting up a reference trigger with zero pretrigger samples will allow you to use this as the start trigger and also continue to trigger each consecutive record. . For scopes, records are taken and stored in the on board memory and then fetched and placed into your computer’s RAM.
There are a few ways to implement sampling on your reference trigger signal, which may take some time and may be complex to implement. I will describe a few ways we can attempt to do this below:
1. One method you could use, and the easiest, is to set a constant record length based on a predetermined maximum high time of your trigger. If you can determine the maximum high time, this would allow you to set what your minimum record length should be on the longest high time expected and take that number of samples as soon as the pulse goes high. For example, if your maximum expected high time of your varying trigger signal is 100us, and you are sampling at 40MS/s, then you would take 100u x 40M = 4000 samples per record. Of course, in the case when your period is 70us you would have some overflow of samples which can be decimated off the end of the record. I am unsure if this will be acceptable in your application, but if you can determine valid samples within your record, this implementation would be the best and would require no additional hardware.
2. Another method would be to create a new sample clock using your onboard clock from one device and external hardware, such as a DAQ card. The method I am thinking of makes use of a counter. Using a counter, you can export your sample clock from one of the 5124’s and input that into the source of the counter on your DAQ/external counter hardware. Then, take your varying trigger signal and place that on the gate of your counter. This would gate your sample clock at your specified trigger frequency so that only when your trigger signal is high will you see pulses come out of the counter. You could then take this signal out of the counter and split the signal with a splitter, then route the clock to both of the clock inputs on each 5124. In this configuration, you would not setup any triggers in your program and would only sample based off your new sample clock. Please refer to the figure below.
Let me know if you have any more questions or if there is anything I posted that was unclear.
Regards,
Kyle S
