Using PFI of PXIe-5442

[Postmodernist]

Hi,
The specification document for the PXIe-5442 mentions that the PFI ports can be used to output a "Sample clock timebase (100 MHz) divided by integer M
(2 ≤ M ≤ 4,194,304)".  However I do not know how to program the PXie-5442 to do this.  I am using LabVIEW 8.0.  How do I do this?

Thanks,

Ben Gilbert

[dansch]

Hi Ben,

To export the sample clock timebase, you can use the "niFgen Export Signal" VI ( found under NI-FGEN » Configuration » Configure Trigger & Synchronization). If you wish to divide this sample clock timebase by an integer M (2 ≤ M ≤ 4,194,304), you will need to set the "Exported Sample Clock Timebase Divisor" property, which will allow you to specify a value to divide the timebase by before exporting. This property can be found by placing down an niFgen Property Node and selecting Routing and Event Configuration » Exported Sample Clock Timebase Divisor. Please see the attached screenshot for a visual represntation of what this looks like in LabVIEW. For more information about the niFgen routing properties and functions, you may refer to the "Programming" section of the NI Signal Generators Help. Hope this helps,

[Postmodernist]

Thanks Daniel,

Your advice worked fine. 

However I neglected to mention that I am also using the PXIe-5442 with the PXIe-5610 (upconverter) to form a PXIe-5672 (rf vector signal generator). 

When I use the devices as vector signal generator I am no longer able to access the divided sample clock. 

For example:

1.    I configure the divided sample clock to output on PFI0 of the PXIe-5442 device.  This works fine.

2.    I output a signal using a RFSG express VI.

3.    PFI is still outputing a signal (which I assume is the sample clock) but it is no divided down.

Is there a way around this?

Thanks,

Ben

[dansch]

Hi Ben,

I am trying to reproduce what you are seeing, but I am slightly confused by a couple of things. When you output the signal using the RFSG Express VI, how are you configuring the 5442 to output the timebase? I found that the timebase continues to be exported by the 5442 when I end my program which uses the niFgen driver, but as soon as I start my RFSG program, the timebase is no longer being exported at all to PFI0. How are you exporting the timebase but also running the RFSG VI? Also, I am interested in learning more about your application and why you are trying to have this divided-down timebase being exported from the AWG. Thanks, and I look forward to hearing back from you soon!

Regards, 

[Postmodernist]

Hi Daniel,

I am conducting some transmission channel experiments.  See attachement: "Setup".  This involves transmitting a periodic signal and determining properties of the channel from the received signal. The transmitter and the receiver are both synchronised to the system clock.  I have been using a NI PXIe system to do this and the results have been good.  I would now like to measure two channels in a piecewise manner.  To do this I would like to use a RF switch to switch between transmit and receive antenna pairs. The transmitter will transmit continuously.  The throwing of the switch will occur after exactly N number of repititions of the transmit signal. In other words the signal throwing the switch must be periodic and synchronous with the transmit signal.  This is why I was interested in using a divided down version of the sample clock.

Regarding my attempts to obtain a divided sample clock on the AWG and use the RFSG at same time, I have attached a VI that does the following:

1.  Set up PFI0 to output a divided sample clock

2.  Use the RFSG

3.  When the RFSG is used, PFI0 now longer outputs a divided sample clock, but does seem to output the sample clock instead.

Is it possible to control the upconverter directly (PXI-5610)? If so I could obtain the functionality of the RFSG while having control over the low level features such as outputting the sample clock. 

Best Regards,

Ben Gilbert

[GRhino]

Hello Ben,

It turns out that there is a magic little VI hidden in the libraries that will help you to solve your problem.  In the niRFSG.lib module found at

{Program Files}\National Instruments\LabVIEW 8.5\instr.lib\niRFSG\niRFSG.llb there is a VI called "niRFSG GetFgen Session" which will provide you with an FGen session handle from the RFSG instrument handle.  That session handle can then be fed into an FGen property node to export the clock and set the divisor.  You can also use that session handle to call the FGen Reset before you close RFSG to kill the exported sample clock.

I gave this a try with a simple tone generator and it seemed to work as you desired.

Regards,

Glenn R.