5641 Timed Loop Error

[creed]

I'm working on a design the requires a 512 tap complex FIR filter.  I have built a 4:1 complex multiplier using the DSP48 slice to fit

the design in the FPGA.  When I compile the multipler by itself (muxCmult1sctlPass.png), It compiles successfully and says the

design will run at > 90MHz.  The version that fails (muxCmult1sctlFail.png) causes a Timed Loop error (SR7301458CodeGenError.png). 

Originally, I got an error message that complained about control and status functions within the SCTL.  When I removed them

"Show Error"  highlighted the SCTL.  I replaced the single SCTL with multiple SCTLs (muxCmultDemuxFxp.png).  "Show Error"

then pointed to the FXP and suggested these be removed from the SCTL.  When I removed them (muxCmultDemux.png),

"Show Error" then pointed to the demux blocks with the same suggesstion of removing them from the SCTL.  When I removed

them (muxCmult.png), "Show Error" pointed to the DSP 48E slices.

Since muxCmult1sctlPass.png compiles with no problem and I've used the DSP48E slice in a SCTL in the past, I'm not sure

what the problem is.

Any thoughts would be appreciated.

As a side question, should I use something other than control and status indicator for IO in VI's that I plan to use as subVIs?

Thanks for your help.

-Chuck

[creed]

So the problem turned out to be that you can't use a wire to pass data between SCTLs at different rates.  It

might be that you can't use a wire even if they are the same rate, but the bottom line was that a wire

can't be used. 

The fix for this is to use a local variable, FIFO or RAM to transfer the data.  This has the unfortunate effect

of adding latency and consuming resources on the FPGA.  

If anyone knows of a way to use an enable to move data though a z-delay/unit delay as well as control the

flow data through an adder that would be very helpful.  This would allow me to run the entire design at the

faster rate and use the enable to mover data at a slower rate where necessary/possile.  Does anyone know

if data flow through arithmetic operators can be controlled by an enable?