About the ADC full scale??

[xy_se]

Hi, this is sunny again.

I got two new questions here:
1. At the beginning of each project, the FPGA resources (I/O, clock, etc)are added to the project in the project explorer and I clicked the property of DAC IQ clock, its frequency is fixed(e.g. 25MHz). Later when various interpolation values are applied to the DAC, the DAC IQ clock shall be changed. But, when I clicked the property of DAC IQ clock again, its frequency is still the original one. So I guess the user doesn't have to care about the clock in the property, it will be changed automatically. Am I right?

2.  what is the full scale voltage of the ADC? I looked at the analog input/output example code, it said that 1.68Vpk-pk is the full scale for I16, so the resolution shall be 0.86/32768. But I looked another example the burst OOK  demodulate VI, it said that "Threshold which is 300 (signed 16 bit fixed point representation for 0.02)" , how come this 0.02 ? I am very confused . So, what is the relationship between the Analog signal and its digital representation? I looked up the datasheet of the ADC but failed to find out it.

Thanks!!

[xy_se]

Follow up...

I just read a article, it seems that LV FPGA 8.5 now supports fixed-point arithmetic operation. Does that mean that I can use fraction number (like 1.2,1.22, etc)in FPGA now just as I found in the burst OOK demodulation example?

[Vinay_Kumar]

Sunny,
1. You are right. The user need not worry about the clock propery. This property is only required for compilation. The Host VI configures the clock at run time.
2. a. IF-RIO has a 14 bit ADC and not 16 bit. Only 14 bits are of use out of the 16 bits of the IQ data. Hence the use of I14.1 representation for I and Q.
    b. (I^2 + Q^2) needs to be  > threshold, to detect the burst. Threshold=300 (I16)= 0.0046 (signed 16.0 format). This is a typo in the doc.
Your approach is right. If you know that your signal amplitude is 0.86, then you can calculate the threshold value and use its I16 equivalent representation to detect the burst.
But if you do not know, 300 seems to work fine. Good question!!

Regarding the follow-up question, you can now represent fractions using fixed point data type in LV 8.5!

Cheers,
--Vinay


Message Edited by Vinay Kumar on 05-22-2008 08:20 AM

Message Edited by Vinay Kumar on 05-22-2008 08:22 AM

[xy_se]

Thank you very much for the quick reply!

I just have one more question regarding to it: Since the ADC is 14bit, and the 14-bit output shall be a signed number, so the range is [-8192,8192]. So what  analog value does 8192 correspond to?(namely, the full scale value) AND, Does the 14-bit value represent the voltage or current or power?


帖子被xy_se在05-22-2008 10:46 AM时编辑过了

[JerryAL]

Hi Sunny

The ADC is 14 bits, but the data type returned is I16, and the data is effectively 16 bit data.  The maximum value to use in the conversion is 32767.

You can think of it two ways.  The first being that the ADC’s 14 bits are using the higher bits of the I16 data type (2 – 15).  What is actually happening is that after the filtering in the digital down-conversion process and conversion to complex data on the ADC, we are getting an extra 2 bits of data in the process which we are still providing as bits 0 and 1.  In a way you can think og it as rounding bits.

So the range is -32767 to +32767 which correspond to about -0.84 Vpk to +8.4 Vpk.

Just to be clear, on the DAC side things are different.  The DACs are 14 bits and the data type is still I16, but the module expects the 14 bits to be in the lower 14 bits of the I16 data type (0 – 13).  If you scale your data to +/- 32767 instead of +/- 8192, you will get distorted signals on the output.

Jerry

[xy_se]

Thank you Jerry sir!

Just one more question.

As for the DAC, what's full scale voltage? I mean, If I send 8192 to the DAC, what's its corresponding output?

[JerryAL]

Hi Sunny

I’ve reprinted the specific section from the module’s specifications.  But basically, -0.4 to +0.4 V corresponds to -8192 to +8192 (I16).

Jerry

Full-scale output range
Using LabVIEW FPGA..............+2 dBm peak (0.8 Vpk-pk) nominal into 50 Ω, –1.5 dBm with sinc and total interpolation factor = 4 at 10 MHz (± 0.5 dB max calibration data uncertainty, <± 1 dB typical without calibration)*

CIC compensation filter lowers the level by 0.59 dB when the total interpolation factor equals 8 and by 0.79 when the total interpolation factor >8.