Configuration of ADC IN PCI 5640R

[KIRAN SIDDANADHAM]

Hello,

This is kiran, currently I am working on the spectrum analyzer for narrow band signals using the NI 5640R,and these are my input signal specifications

Fc = 21.4MHz
BandWidth = 50k(narrow band)
Sampling Rate should be 120960(after converting into baseband signal)



I have a few doubts regarding the configuration of ADC.

1) How to configure the output sampling rate from ADC(FPGA Input) to 120960?

2) What is minimum sampling rate that can be achieved by the ADC and How?

3) From the NI 5640R specifications document it is given that


                         Decimation

                        Using NI-5640R driver............... ÷4 to ÷2,048
                        Using LabVIEW FPGA ............. ÷4 to ÷32,768*

and

                        from the AD6654 datasheet it is given that The decimation ratio should be 2 to 32.

How these things will be matched ?


4)In the example VI ADC Config DDC.vi some pre defined decimations & filter coefficients  are represented.How to get these coefficients if the configuration differs?


5) I have a little bit confusion with the block diagram which I have attached,

VCXO(200MHz) is divided with the N0 that is sent ot the PLL clock with M/N and later to the decimation and then to the FPGA

Here N0 will be 2 gives the 100MHz to the ADC.So, Input data rate will be 100Ms/sec.What changes will be done if we configure the M & N ? Will it effects the data rate?and what for PLL_CLK is used?

Regards,

KIRAN KUMAR S