ERROR:HDLParsers:3370 Compile Error when compiling for NI-5640R

[astromike]

I'm trying to get a FFT Core working inside the NI-5640R FPGA.  In my latest debugging step, I have received the following error when compiling:

Compiling vhdl file "C:/NIFPGA82/srvrTmp/LOCALH~1/IFBC3E~1/bushold.vhd" in Library work.
Entity <bushold> compiled.
ERROR:HDLParsers:3370 - "C:/NIFPGA82/srvrTmp/LOCALH~1/IFBC3E~1/bushold.vhd" Line 142. Value 0 is not included in the range, 1 to 2147483647, of kConfiguration_ClkMaxWidth.
ERROR:HDLParsers:3370 - "C:/NIFPGA82/srvrTmp/LOCALH~1/IFBC3E~1/bushold.vhd" Line 143. Value 0 is not included in the range, 1 to 2147483647, of kConfiguration_ClkCounterWidth.

Has anybody seen this before?  I am including my FPGA VI that is causing this error (FFT (FPGA).vi).  I am also including my previous step in debugging the FFT that worked (FFTworking (FPGA).vi).

[astromike]

I removed the Replace Array Subset and tested just the creation of the 4k array.  The error dissappeared, so there may be something wrong with the Replace Array Subset in v8.2 of the FPGA Module.  However, I don't think creating a 4k array of 32-bit integers is a smart idea with the FPGA.  I started the compile at 16:20 Thursday afternoon, and at 05:50 Friday morning, the compiler croaked.  I found no useful information in the output, the output looked like the standard build output was paused and a NI message saying to contact ni.com/support appeared.  I do not plan on repeating this problem.

[Tunde_A]

Hi,

The main cause of this error message is the large array size. You configured a 16-bit fixed-size array with 4096 element for a total array size of 65536 (16 * 4096). Array uses a lot of FPGA resource and the general recommendation to limit the use and size of array as much as possible on the FPGA VI. This VI will certainly overmap the FPGA resource because of the large array size.

Although this error message is not directly related to the array size, it has however been reported to R&D (#4G3COBJ0) for further investigation. A possible workaround would be to reduce the size of the array or use DMA FIFO to pass the data to the host.

Thanks for the feedback!

Tunde A.

LabVIEW FPGA