Error DIO on 5640r with labview 8.5

[JerryAL]

Yes, there is a known issue and is caused by LabVIEW DSP 2.5 overwriting a necessary elemental I/O VI called EIO_SpecifyEIONode.vi.  Repairing LabVIEW FPGA with the installer should fix the issue.  (If you reinstall NI DSP and see the issue again.)

If repairing LabVIEW FPGA does not fix the issue, then you can email me with the above email and I can send you a VI to replace to which should allow you to use NI DSP.

Jerry

[SebastiaanNL]

Hi Jerry,

I think you have found the origin of my problems. Unfortunately, I found that out by an error that occured during the repair of Labview 8.5 FPGA Compile Server. I've attached a screenshot of the error to this post to make clear what the error message said (don't mind the background wallpaper). Because of the error during the repair, the problem still exist when I try to compile FPGA programs with I/O blocks in it. Hopefully you or anybody else knows a way to solve this install error, I will look for a solution myself also.

Thanks for all the support already.

Regards, Sebastiaan.


Message Edited by SebastiaanNL on 03-06-2008 04:33 AM

[luchigno]

Hi Jerry, thank you for all..

I have another question for you: is it possible to integrate the "xilinx system generator for dsp" into labview fpga also for the ni5640r series?

thanks...

[sree_405]

Hi Lichigno ,

I am Sreenivasulu.
I have started working on NI-5640R LabVIEW card.I am able to do simulations using
labview8.2. But I am unable to interact with NI-5640R to get the
output through output ports.I studied the manual given by NI. But I am confused fully
with the procedure and i did not understand.I tried the example projects ni5640R,but I
failed.

So please tell me the procedure to be followed, how the ni5640R card ADC and DAC
working(how to give I/P to ADC and how to get the O/P from DAC),and how to interface
host(my PC)and Target(ni5640R) using VIs.
Please tell me that how the signal flows(inter connection between)through the parts of
VI(both in HOST and FPGA modules).

Final my goal is i need to generate modulated(AM,FM,FSk,BPSK,QPSK Etc) signal with Fc
21.4MHz for providing as a input to other module(RAD-2,Pentaland).
plz tell me sir your own procedure i'll follow or tell me can i get this by using
LabVIEWmathscript or modulation tool kit Etc.

I am using LabVIEW 8.2 and card NI-5640R(PCI based) v 1.1

           Thanking you so much sir.


Thanks & regards,
Sreenivasulu.O

[JerryAL]

Hi luchigno,

Sorry for the late response.  This is something I had to ask a real LV FPGA expert about.  (My expertise falls more to the hardware side of the ni5640R module.)  Xilinx system generator is a high -level tool for designing high-performance DSP systems using FPGAs.  You can incorporate the VHDL code generated by the tool to LVFPGA using the HDL node.

Here is a white paper that shows how to integrate such model into LVFPGA:
http://zone.ni.com/devzone/cda/tut/p/id/2817

I hope this helps.
Jerry

[Tunde_A]

Hi Sebastiaan,

I would suggest you first uninstall the "Compile Server" then reinstall it again rather a repair

Tunde A.

[SebastiaanNL]

Hi Tunde A.,

Thanks for your help. I've tried your solution already, but it didn't help. Luckely, I did solve the problem, only it took a lot of effort. I concluded that the problem was in my registry, since the same problem did not come up by colleague's of me. I had to re-install my entire PC to solve the problem, but finally it works now.