Hi,
Has anyone has encountered any problems while running the 'NI5640R IQ Output' example ? Wondering if we're missing something...
In the example ‘Ni5640R IQ Output (HOST)’ the following error is displayed after successful execution for a while:
Error –2
occurred at ni5640R DAC Wait Until Serial Ready.vi
Possible reasons(s): Timeout
This seems related to a FIFO wait condition in “Purge Output FIFOs” sub-VI” – needs further evaluation. If the FPGA is not reprogrammed after this, the following error is seen to occur:
Error -61046 occurred at ni5640R
IQ Output
Possible reason(s): LabVIEW FPGA: (Hex
0xFFFF118A) An error was detected in the communication between the host
computer and the FPGA target.
Thanks,
-Manik