FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.17

[pd2]

I have got "FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.17" twice now during FPGA compiles. Oddly enough, the first time it happened, a new compile attempt was all it took to fix it. I am recompiling now after it happened after a compile of a new design. Any idea how to fix it?

I'll attach the compiler output.

Edit: The smiley above is a colon then a capital P.

Message Edited by pd2 on 06-23-2008 02:08 PM

[pd2]

As before, a recompile worked fine. Hopefully this can be fixed sometime, but for now, my workaround is to just recompile.

[pd2]

I changed the type of some wires from arrays of I16 to arrays of I32. Now I get a different error:

ERROR:Xflow - Program par returned error code 1. Aborting flow execution...

Any ideas?

I'll attach the compile log again and try recompiling.

[pd2]

It worked fine for the recompile. Very strange.

[pd2]

I keep getting error after error. I tried the "-keep_hierarchy SOFT" option from http://digital.ni.com/public.nsf/allkb/3737F8EB7179A206862572EC0073A3E9, and it helped a little. I was able to do a sucessful compile after this, but I keep getting more errors.

Here are the two latest error messages:

(last part of compile text)
FATAL_ERROR:Portability:PortDynamicLib.c:358:1.27 - dll open of library <> failed due to an unknown reason. Process will terminate. For more information on this error, please consult the Answers Database or open a WebCase with this project attached at http://www.xilinx.com/support.
ERROR:Xflow - Program xst returned error code 91. Aborting flow execution...

Then I tried a recompile and didn't get any compile text. I only got a message box which said:

xflow.exe - Entry Point Not Found
The procedure entry point ?get_vendor@PM_PIC@@QBEQADXZ could not be located in the dynamic link library libPersonalityModule.dll.

What should I do to try to resolve all these errors?

[pd2]

A recompile attempt just got the same message box.

[pd2]

It appears that these errors only happen when I have a timed loop clocked to an ADC sample clock.

To add the clock to the project, I right-click FPGA Target (PCI-5640R) then click New->FPGA Base Clock. Then in the dialog box, I click the Resource drop-down menu and select the ADC clock. I then click OK. Is there something wrong with this procedure? Should I be changing some settings in the dialog box or something?

[pd2]

Actually, it works sometimes with the clock; so this is not the only indicator of whether the compile will pass or fail.

[JerryAL]

Hi PD2

First, in terms of adding and configuring a clock to the project, the method you state should be OK.

Concerning the errors you are getting, I have not run into them before.  My expertise with this module is coming more from the RF side of the module that the FPGA side.  I looked at your VI though, and I am not comfortable with the way you have configured your filters, mainly the use of arrays.  Also the multiple arrays in inside a cluster.  I have not been that successful writing code like this before so I am not sure how feasible this is when compiling.  One suggestion I have to see if this is an issue or not would be to reduce the size of the arrays down to three elements each. I know this will not be a feasible filer for you, but if the code starts compiling without any errors, it may be a sign that the code might be a little complex for the compiler.  Also, the fact that you seem to be running a 75 tap filter, and twice, might be too much for the compiler for the IF-RIO’s FPGA.

I’ve attached a filter that we have implemented in two projects here.  It is very pipelined as well as reusing multipliers.  The VI must run in a SCTL loop that is running at least as twice as fast as the ADC IQ rate.  This is due to a MUX internal that switches whether an I or Q sample is directed to the multipliers.  In this way, the multipliers on the FPGA do double duty, and we minimize the number of multipliers used.

The other important feature to point out about the code is that the coefficients of the filter are “clocked” into the FPGA at the beginning through one front panel control (vs. an array) before processing starts.  Also, the coefficients in the array. The array manipulation itself, are not processed though every clock of the SCTL loop. 

The compilers should spread out every element of the arrays and arrays in the clusters to individual data lines so that the data can process on every cycle of the clock.  But I have had issues in the past where I have used clusters and I have been unable to compile the code.  I usually minimize the use of clusters and arrays that I now use, especially when putting arrays in clusters.

I hope this helps.
Jerry

Message Edited by Jerry_L on 07-07-2008 11:30 AM

[pd2]

Thank you for this example. I do wish the FPGA side of things was more documented. I will base my future work on the style of the example you provided. That should help with the errors. I'll let you know if I continue to have problems or if I need more help.