FPGA Memory

[Tai Wei]

Good day,

We have been doing some data capture using the various examples files that come with the board.    We would like to implement a PM/PSK demodulator for continuous data demodulation.

1.   How do I use the 2M of SRAM connected to the IF-RIO?

2.   For FIFO operation, how does it work, I would like to stream continuously data from the IF DDC to the demodulator toolkit for continuous PM/PSK demodulation.     The examples use the full signal, but I hope internally, the FIFOs are using something less than FULL to ensure adequate time for the host VI to load/unload data from the FPGA.

3.   I notice a small frequency offset in the frequency spectrum of the captured signal.    I traced the VI and believe that the board is probably lock to an unstabilesed VCXO.     How do I configure the board to use a more stable external OCXO on the clock in port?

Thanks and best regards,

Tai Wei

[JerryAL]

1. There will not be support for the SRAM on the first version of the IF-RIO.

2. There are no other flags on the FIFOs other than the "full" flag. However, using DMA you should be able to keep up with data rate. The fastest way to unload data from the FIFO (from the Host VI) is to wire the "elementsremaining" out of the "Read" to a shift register, and on the next iteration of the loop, wire the shift register to the "number of elements". Also check that you have not overflowed the FIFO.

<See the attached image, ifrio-fifo.jpg for more info.>

Doing this you can unload data from the board very quickly. However, I'm not sure how fast the demodulation algorithm is.

3. Do both the analyzer and the generator sharing a reference clock? If not, then the frequency offset is expected. Anyway, you can use the front panel connector labeled "CLK IN" to send in a reference clock or a sample clock. Then use the VI named "Configure Timebase" to configure the board to use the front panel connector.

[Tai Wei]

Thanks Jerry,

Yes, will modify the DMA operation to see if we can squeeze any more from the card.    We note that the DMA FIFO is directly taking up the FPGA space, as such, if we put a few 10s K word of FIFO, the FPGA would reach 100% full and there would be no more space for processing.     As such, if we could off load memory to external SRAM, and use the FPGA only for logic operations, it would improve the value of card.

In DMA mode, when I increase decimation, the card becomes real time, which is reasonable as the amount of data reduces.     However, if I increase the decimation further, the card again becomes non real time.     This last part is something I do not quite understand.

We are monitoring a signal source (Telecommand/Telemetry Processor) that has its own OCXO.    The center frequency of the source is accurate, as verified with Agilent PSA/VSG.    We are already using a 10 MHz from an Agilent instrument into the SMB CLK IN, but we are not too familiar with the VI to configure the clock source for external clk input.    The names used in the VI does not correspond closely with the TI and AD data sheets.    It would be most useful If you could post a screen shot of the VI settings and/or a more detailed information on what each button on the clock config VI do.

Thanks again and best regards,
Tai Wei

[pranavhp]

Jerry,

Is there any possibility of using PC's DDR RAM as bigger FIFO?

I know that Virtex II pro has PowerPC and DDR controller.

Thank you.