Hi,
I have an application with PCI 7833R FPGA board. It reads ADC data, process it (with phase delay, FIR filter, etc.) and then output to DAC. It works fine. Late, we added an UART/RS-232 interface to output the processed data through serial line in parallel with DAC. The UART module has one Tx line and one Rx. The whole design is HDL based. It is actually written in Verilog, compiled to .ngc file and embedded in the FPGA VI. The FPGA VI is quite simple, a single clock timed WHILE loop with a timer sequence inside (for ADC sampling control).
The problem is the code can not read the UART Rx input pin. I brought out a few test points and one of them is the feedback of input signal. The result is the Rx pin never read the external signal, no matter where the DIO Input pin of FPGA I/O Note sits, inside the timed sequence, out of the sequence, even out of the WHILE loop. I have tried various options of synchronization for the DIO input pins, auto, 0/1/2. No help.
I eventuall found out (by writing small HDL codes and VIs for testing) that it can read only when it is in a separate single clock timed WHILE loop. But, if doing so, I have to break up my codes, then bring a whole bunch of data (there are 6 channels of ADC/DAC path, each chnannel has its own UART port) from the WHILE loop where ADC/DAC sit to this separate WHILE loop. A quick test for a single bit data travelling between WHILE loops shows a delay of 10 clock cycles or 250ns.
I called NI support and was told that DIO input with 0 synchronization should read external every clock tick, it does not matter if the pin is located in the sequence or in the WHILE loop. Well, it is supposed to be and it is what I thought. But it never work for me.
Any help is very appreciated.
-Wenwei
