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PCI 5640R using Both ADCs

Oops...I failed to get this post on the IF-RIO board the first time around.  Sorry about the other posting!
 
Hi,
 
I am having a difficulty acquiring data from both ADCs on the PCI-5640R.  I started with the My Simple Spectrum Analyzer example in the User Guide tutorial and then added the second channel to it as seen in the figure.  I didn't observe any errors, but the second FIFO (FIFO 1) comes back empty.  Maybe I need ADC1 acquisition to occur in it's own timed loop with the ADC1_clk driving it?  Maybe the problem is in the Host VI where I signal for acquisition and then read from FIFO before FIFO1?  I'm hoping someone can provide an example to save me compile time in trying to guess my way through it.  There must be a lot of people using both inputs!
 
Chris
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Hi Chris

You can put the ADC nodes in the same Single Cycle Timed Loop, but the ADCs must be synchronized to use the same clock for both.  I’m also assuming you are configuring both channel in the host.

You can find information on synchronizing the clock in this thread: (specifically the post on 02-07-2007 10:18 AM)

http://forums.ni.com/ni/board/message?board.id=ifrio&thread.id=287

Sorry, I don’t currently have an example….

Jerry

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Hi Jerry,
 
I followed the instructions in that post...everything seemed to go well.  I am using two FIFOs for DMA memory access, and the second one (FIFO1) returns empty.  I'll include the HOST and FPGA code in images below so that you might be able to find a glaring mistake.  I suspect I may still be using some configuration remnant from the original tutorial that needs to be eliminated now that we are using both ADCs.
 
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When I say the FIFO1 is "empty," I mean filled with exactly 5000 0s.  On the PCI-5640R, I have DAC0 fed into ADC0 and DAC1 fed into ADC1.  The DAC outputs are working fine.
 
Chris
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Ah,  Moved the Config.ADC Simultaneous Programming right up front (following the OPEN FPGA VI Reference) and it works fine.
 
Thanks for the help, Jerry!
 
Chris
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Hi Chris
 
I'm glad you got it working.
 
If you don't mind, can you send me your example?  I can take a few minutes to make any changes I think it migh tneed and re-post it. 
 
The only issue I have right now is that I am set up for LabVIEW 8.5....
 
If you want to still send it, please send it to ni5640r.support@ni.com
 
Thanks
Jerry
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Jerry,
 
I'll be glad to send it to you.  It still has one bug which I am sure you can help me with.  With the DACs set to 32 MHz and 30 MHz, respectively and the ADC (jointly) set to 30.5 MHz, I am observing DDC outputs of 0.75 MHz and 0.25 MHz, respectively.  Half of what they should be.  Any idea what is going on?
 
Chris
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Oh, and one more question (which probably should have gone on a separate post)...
 
Everytime I save the project, quit, and return to it, the typedef is screwed up and the FPGA VI Reference is broken.  I have to disable the "Bind to Typedef" and re-enable it to get it to work EVERY TIME!
 
Chris
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Hi Chris,

Can you be a little more specific about this issue and what you are doing, and what you expect to see?

Are those the frequencies of CW tones?  Are you tieing the two DAC outputs together? etc/

Thanks

Jerry

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Jerry,
 
Reference the image HOSTleft above to see my HOST configuration (with the understanding that I moved the Config.ADC Sim Prog).  The ADC NCO frequency is set to 30.5 MHz.  Frequency0 is set to 32 MHz and, therefore, DAC0 outputs a 32 MHz tone.  I have that DAC0 tone connected directly back into ADC0 with a short SMA-SMA cable.  In the plot, I expect the frequency of the DDC'd signal to appear at 32-30.5 = 1.5 MHz, but the FFT shows it to be at half that value, 0.75 MHz.  Similar issue with DAC1 => ADC1.  You can see from the images of post 01-16-2008 03:30 PM my current configuration which was modified from the My Simple Spectrum Analyzer (project) tutorial for the IF-RIO...the results from the tutorial were as expected.  An input at 32 MHz, when passed through the NCO of 30.5 MHz, gives an FFT spike at 1.5 MHz.
 
Chris
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