Phase calculation from RF signal

[aalim]

Hi all,

I am trying to calculate phase between two RF signals (both at 40MHz & 40.1MHz) by using PCI-5640R FPGA but i am getting the desired phase vales and its givening some abrupt phase jumps which is not expected. I just want to explain how i am trying: -->> initially i am applying one 40MHz signal to AI Ch0 and AI Ch1 and bothe the Channels (Ch0 &Ch1) provides me I & Q signals, these four I&Q (two from each Channel) signals i am  forwarding to HOST and then calculating their phases likewise....

  theta 1= Q/I, for channel Ch0

     theta2 = Q/I, for channel Ch1

and phase difference between two channels, theta = theta1- theta2.

I  have unwraped the phase and plot it Vs time, still getting phase jump. 

Does anybody have an idea how to fix this issue? Any help would be highly appreciated.

I am using Labview8.6.1, NI PCI-5640R FPGA (Device Driver 1.5), Windows XP.

regard

Aalim

[JVP]

Hello Aalim,

Would it be possible for you to post your host VI? Also, on the FPGA side did you start of with an example or did you write the VI from scratch? Have you PLL the ADC clocks for synchronization? Would it be possible for you to get me information about the PC that the PCI-5640R is in?

Best Regards,

Jignesh P

Applications Engineer

[aalim]

Hi Jignesh,

here are the answers for your questions:

I have atached my host vi.

I started my FPGA VI by modifting shipping example.

I did not PLL the ADC clocks for synchronization (in timebase vi), but Applied soft synchronization(in ADC Syns vi). 

Information Regarding PC: Windows XP, Sp2, core2duo cpu @3.16GHz 3.17Ghz, 3.24RAM

Regards

Aalim

[JVP]

Hi Aalim,

Since you have modified the FPGA portion as well, could you attach your project, I would like to see what you have done there as well. I am setting up some hardware on my end to test something on my end as well. If I had your entire project along with the LabVIEW bit file that would make it easier on my end.

Best Regards,

Jignesh P

Applications Engineer

[aalim]

hi jignesh

sorry for delayed response. you send me your email, i will forward you the vis. can you give me more details about what are you doing at your end?

[JVP]

Hi Aalim,

In the eairler post you mentioned doing a software pll, I am not sure what you meant by that. But I have something you can do, that will give you a Hardware PLL. Please see the image below. The modification will be on the host VI.

Please let me know if you have any questions.

Best Regards,

Jignesh P

Appliations Engineer

[aalim]

Hi Jignesh ,

In the earlier post I have mentioned doing a software pll mean is the same what you have said and the only difference is that I was using ADC syns.vi while you have used config timebase.vi. Thank you for this valuables post, now i want to test these changes in my vis and then will let you know the results.

regards 

Aalim