Phase lock loop (PLL) for frequency multiplication (angular encoder interpolation)

[sigmakappa]

Hi you all

I measure the angular position (crank angle of a CI engine) by acquiring the signal of an angular encoder (photointerrupter on a slotted disk with 900 slots/rev. = 0.4° resolution). In order to interpolate the angular postion (to get a better resolution for controlling the intake/exhaust valves of the CI engine precisely) the idea is to use some sort of PLL to track the encoder signal (TTL) and generate a (locked) signal with a frequency which is four times the frequency of the encoder signal (= 3600 pulses/rev. = 0.1° resolution). Since a cRIO-9082 is used for control purposes anyway I prefer to implement the PLL on its FPGA directly (with a NI 9401 for the TTL input of the encoder signals) without using any third-party hardware. Fortunately I found a PLL implementation (Costas loop) from the LabVIEW FPGA RF Communication Library 2.1 and tested it successfully with simulated (noiseless) square wave signals. Due to fabrication tolerances of the slotted disk the frequency of the real encoder signal is not perfectly constant (at a constant rotational speed) which might be a problem for the PLL (maybe a general problem or just a matter of tuning the PLL parameters (e.g. filter parameter) etc.

Since my knowledge in this field is very limited (DSP in general) I would like to ask some questions here:

1. Is using a PLL a reasonable approach for such an application or are there other methods to achieve such a frequency multiplication (i.e. position interpolation) of a square wave signal (e.g. with a second optical sensor I could create some sort of quadrature encoder but I try to get along with the existing hardware if possible)?
2. I think the mentioned PLL implementation (niFPGARFv2 PLL.vi) is normally used with sinusoidal input signals thus I wonder if there are any drawbacks if it is used with square wave signals (e.g. due to high frequency components etc.). Currently I am converting the digital input signal (low/high) to a -1/+1 square wave and feeding it into the PLL. Maybe a PLL for a digital input signal could be implemented more easily (e.g. the phase detector etc.) but I could not find any starting point for such an implementation.
3. If the PLL (VCO) needs to run at a multiple of the input frequency (i.e. four times the input frequency) some sort of frequency divider is needed in the feed back path of the PLL control loop (i.e. the phase of the VCO needs to be divided before it is fed back to the phase detector or something like that). Is this basically correct?

(The rotational speed will be in a range from 200 to 1800 rev./min hence the frequency of the encoder signal (CDM) is around 3 to 27 kHz but only operating points with constant speed need to be considered.)

Any help and advice is highly appreciated.
Thanks a lot!

[Christoph_D]

Hi,

I dont know the implementation you are refering to, but I guess they assume a signal of constant frequency, so I cant tell you if there are any drawbacks in using this implementation.

As far as I understand you want to quadruple your input frequency (digital signal). So the easiest implemtation I could think of is that you have two loops:

1. First one measures the ticks (iTicksInput) between two edges of your input task
2. The other loop generates a output signal with a variable period. The period should be in your case iTicksOutput=iTicksInput/4. Every time the loop starts a new cycle the value of iTicksInput should be read and iTicksOutput is updated.

In my scenario the phase of the output wont be synchronous with your signal.

Best regards,

Christoph