IF-RIO
Pipilined block with latches driven by different clock in FPGA
Hi,
Thanks for the previous help. I have made some progress using Labview FPGA. Actually, I have had a CORDIC running in the 5640R FPGA. However, the CORDIC I just implemented is unrolled bit-parallel pipelined FPGA which consumes too many slices on the FPGA. Now I turned to implement a bit-serial pipelined architecture and I met the following programming problem.
The architecture I want to implement is in the attached.
The blue blocks are combinatorial logic. In ths previous design, there are several large block between each latches in red. Say, the red latch latches every 24 ms. In order to implement bit-serial, I have to divide one large block into four smaller block and implement mux and demux. Now I had 5 new latches in green, each latches every 4 ms.
Any hints on how to programme this structure into Labview? I would really appreciate the help.
David
ps: The second attached picutre is the unfinished code for the small block.
.
Thanks for the previous help. I have made some progress using Labview FPGA. Actually, I have had a CORDIC running in the 5640R FPGA. However, the CORDIC I just implemented is unrolled bit-parallel pipelined FPGA which consumes too many slices on the FPGA. Now I turned to implement a bit-serial pipelined architecture and I met the following programming problem.
The architecture I want to implement is in the attached.
The blue blocks are combinatorial logic. In ths previous design, there are several large block between each latches in red. Say, the red latch latches every 24 ms. In order to implement bit-serial, I have to divide one large block into four smaller block and implement mux and demux. Now I had 5 new latches in green, each latches every 4 ms.
Any hints on how to programme this structure into Labview? I would really appreciate the help.
David
ps: The second attached picutre is the unfinished code for the small block.
.
You should use a Single-Cycle Timed Loop to have more control over the timing of your code. You can use feedback nodes or shift registers as registers and case structures or the select tool to determine what gets written to the registers and when.
I envision your code to look something more like this:
Regards,
Joseph D.
Message Edited by jdigiova on 04-17-2007 04:52 PM
