Port A Error

[Ex-NISH2]

I got the following error message during the compile:

...

Regenerating IP...
ERROR:coreutil - Failure to set parameters on core: Illegal combination: Port A
   Width and Port A Depth
ERROR:coreutil - Failure to generate output products

...

I don't know what does this 'Port A' mean and how to fix it.

I am using LV 8.20 and IF RIO 1.0.  I installed by following steps:

1. Copy C:\Program Files\National Instruments\LabVIEW 8.0\instr.lib\ni5640R
   to   C:\Program Files\National Instruments\LabVIEW 8.2\instr.lib\ni5640R
2. Copy C:\Program Files\National Instruments\LabVIEW 8.0\Targets\NI\FPGA\PCI-5640R
   to   C:\Program Files\National Instruments\LabVIEW 8.2\Targets\NI\FPGA\PCI-5640R
3. Copy C:\Program Files\National Instruments\LabVIEW 8.0\vi.lib\LabVIEW Targets\FPGA\PCI-5640R
   to   C:\Program Files\National Instruments\LabVIEW 8.2\vi.lib\LabVIEW Targets\FPGA\PCI-5640R
4. Copy C:\Program Files\National Instruments\LabVIEW 8.0\examples\FPGA\NI-5640R
   to   C:\Program Files\National Instruments\LabVIEW 8.2\examples\FPGA\NI-5640R
5. Run  C:\Program Files\National Instruments\LabVIEW 8.2\Targets\NI\FPGA\bin\lvfpga_make_resource_cache.exe

[Ex-NISH2]

I found the reason, but very strange.  It is due to an I32 memory with depth=1.

When I set target as 5640R, I creat a I32 memory with depth=1.  Read the address 0 in an infinit loop.  Compile it.  You get the Port A error.

When I set the depth =2 or =6, it is OK.

It happens to I16 and U32 too.  But it is OK with boolean.

Hope I catch a bug.

[JerryAL]

Hi Ex-NISH2

It sort of is a bug indirectly.  The Xilinx tools do not support a depth of 1, so we need to remove it from the capability from the dialog or put in code that replaces the memory block with a register in this case.

The only work around at this point is use some other "register" to hold the value such as locals, globals, fifos, feedback nodes, etc...

Jerry

[Ex-NISH2]

I am passing start stop through VIs with memories.  It can work with SCTL and different clock domain.  Can Global do the same thing?

BTW, boolean memory can not set depth=1 either.

[Mr._Jim]

Hi Folks,

I'm resurrecting this thread because I just saw this anomaly crop up in NI FPGA 8.5, and it was pretty cryptic to track down.  I increased the depth of the memory and the problem went away.  To make this information easier to find for others, here's the full text of the error message that appears:

ERROR:coreutil - An error occurred while running Java. Please examine the

   console or coregen log file for a specific IP related error.
   If there is no specific error the problem may be due to memory limitations.

   For more information please consult solution record 21955 available from:
   http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=21955Finished Regenerating.
ERROR:sim:57 - Error found during generation

May I humbly suggest the following?:
1.    Is there a way to change the NI FPGA implementation of the memory allocation such that a depth of 1 doesn't cause any issue?  (Even by allocating a depth of 2 behind the scenes with a dummy element)

2.    Would it make sense to only permit users to enter 2 or more in the depth field on the Memory Properties dialog, possibly with an explanation?

Thanks in advance,

Jim