Using DAC0/DAC1 as I/Q baseband channel to work with zero-IF architecture RF front end

[david uang]

    Hi,

     I am using the 5640R FPGA card together with RF front-end to transmit and receive OFDM modulated signal. (something similar to 802.11). I was working with a low-IF architecure RF front-end (NI PXI 1042) and now I need to modify my design to work with a zero-IF(direct downconversion) architecture RF front-end.
   Therefore, I need to generate both I and Q baseband analog signal which I will use as the input to the RF front-end.  Thus, I need to gurantee the I and Q channel (ADC0/ADC1, or DAC0./DAC1) are both synchornized.
   I read Mauricio's post about synchronizing the two DAC and two ADC, in his response to the filtering with IF-RIO. It helps a lot. Yet I still have some questions. Advices would be greatly appreciated.

    If I want to synchornize ADC0 and ADC1, should I put a "ADC reset" vi in the host after I finish the DAC configuration VI? Besides, I could not find anything similar to the "Profile" used in the DAC configuration. Since DAC reset will reset the profile 0 which is undesired as discussed in the previous post, I am wondring if there is anything similar to the ADC.

   Besides, to get the received I/Q based band data, should I just read the ADC_0_Port_I and ADC_0_Port_Q? I will later set the Transmit Frequency and Receive Frequency to both 0M. Is there anything that I should do in addition to what Mauricio kindly listed in his post?

   I attached the picture of what I did to the Host VI and FPGA VI.

   Thanks a lot.

David

[david uang]

I should elaborate a little more about what I am doing.
I will generate and do the frequency-time conversion(IFFT) of the OFDM signal in the FPGA and also do the packet detection, timing synchronization, FFT in the FPGA. The signal will occupy 12.5MHz Bandwidth (I choose as a convenience since it is the supported clock rate of ADC and DAC.). The OFDM carrier near DC is not used.

[david uang]

Hi,

   I was not able to run my vi after I clocked the configuration loop with RTSI_Ref_Clk and also did the other step as illustrated in "filtering with..." post.  A error -61046 occured with the following message.


  Error -61046 occurred at ni5640R Template (HOST).vi

   Possible reason(s):

    LabVIEW FPGA:  An error was detected in the communication between the host computer and the FPGA target.

    If you are using any external clocks, make sure they are connected and within the supported specifications. Also, verify that the rate of any external clocks match the specified clock rates. If you are generating your clocks internally, please contact National Instruments Technical Support.


   The attached .zip file is my coded project.

   Advice is greatly appreciated...Thanks.

David

[Mauricio Capistran-Garza]

Hi David,

I'm afraid you will not be able to use this board for a zero-IF architecture since all the signals are AC coupled. The lowest frequency signals that you will be able to acquire/generate without being affected by the front-end filter are at 250 kHz. If this is still an option for you then we can try to figure out why you are getting that error.

- Mauricio

[david uang]

Hi Mauricio,

    Thank you. I do not use DC and could avoid using subcarriers near DC for my OFDM signal. Basically my purpose to set up this test bed is to test analog impairment including IQ mismatch. 
    Is there any else information should I supply?
  
Regards,

David

Message Edited by david uang on 09-06-2007 07:04 PM