What is the maximum throughput of ADC channels into the FPGA (PXIe-5641R)?

[mcostolo]

I've got a PXIe-5641R board.  I *want* to sample two independent signals on the two AI channels of the board at the full 100 MS/s A/D rate but understand I'm limited to 25 MS/s because of the factor of 4 decimation.  (This makes me wonder where the 100 MS/s A/D spec comes from.)  My question is, does this 25Ms/s get multiplexed between the two AI channels, or can each AI channel (after DDC) send data to the FPGA at the 25 MS/s rate?

[JerryAL]

Hi

he ADCs sample the data at 100 MSps, the default configuration. The 25 MSps is a result of the Digital Down Conversion stage where the signal is multiplied by a NCO Sin/Cos, filtered and decimated down to 25 MSps. Each ADC can send IQ data to the FPGA at 25 MSps as there are dedicated lines to the FPGA for each ADC. The same is true for the DAC side.

Jerry

[mcostolo]

Thanks Jerry.