can't write data to 5640r FIFO/memory

[Tunde_A]

Hi,

You are correct that there is a synchronization issue between the host VI and the FPGA VI. Looking at your host VI example, it seems the "Open FPGAVI Reference" is set to "open and run" the FPGA followed by FIFO depth configuration and FIFO write. The implication of this is that the FPGA VI will start executing immediately.

I will suggest you set the "Open FPGA VI Reference" option to "open", followed by FIFO depth configuration and FIFO write, then the invoke node to "run" the FPGA. Afterward subsequent FIFO write can be handled in a loop as illustrated below.

Another option will be to set the timeout value for the "DMA FIFO Read" on the FPGA VI to -1 in order to wait until data is available in the FIFO (or a reasonable timeout value). However, this option will only be possible in a WHILE loop or outside the Single Cycle Timed Loop (SCTL) but not in a SCTL. SCTL does not support any form of wait functionality.

Tunde A.

Message Edited by Tunde A on 02-06-2008 01:43 PM

[ksalexander]

Oh!!!!  That is perfect, i'll try that out ASAP.  Something so simple!!!

[ksalexander]

Thank you, that was exactly the problem.  Everything works as expected now.