Hey Stu,
You have a number of questions, and I will try to answer all of them,
but I think it might be clearest if I just explain the whole situation. Forgive
my verbose response, but I want to make sure you have your questions completely
answered. The answers to your questions somewhat depend on the version of
LabVIEW that you are using because of some improvements that we made in LabVIEW
2010 (and later versions).
If you are using LabVIEW 2009 (or older):
Typically the reason why you see the broken wire between the "Open
FPGA VI Reference" and the first template VI is because of a mismatch in
the bitfile path in the two nodes. This can occur when VIs or projects are
moved, or if they are installed to a different path from which they were last
located (or a few other reasons). For example, copying the template stack
("NI-5640R VIs") to a new location can cause this to happen. However,
there is a much simpler way to repair your project than opening up all of the
host VIs and replacing controls. In the configuration dialog for the Open FPGA
VI Reference, there is a checkbox and path to "Bind FPGA host reference to
type definition". All of the template VIs controls have already been bound
to this single typedef and can be updated with one simple step. Check the
checkbox and browse to the "NI-5640R VIs" directory in the specific
project you are working on. In that directory you should see "ni5640R
FPGA VI Reference.ctl". Make sure you are pointing to the right copy of
the control on your system or you will overwrite one associated with another
project and break the other project instead. Select this control, then click OK
in the configuration dialog for the Open FPGA VI Reference. When you do this,
LabVIEW will go to all instances bound to this typedef and update them with the
new bitfile path (which you saw in the configuration dialog). The updating can
take anywhere from 10 seconds to a couple minutes if you have a really slow/old
system.
If the bind to typedef doesn't work, there are a few common mistakes
that you might watch out for.
1) Make sure your "ni5640R FPGA VI Reference.ctl" is not
marked read-only. This would prevent LabVIEW from making necessary edits. This
is usually easy to spot by opening up the configuration dialog for the Open
FPGA VI Reference and checking the path field under the bind to typedef
checkbox. If the path is blank and you do not see the path that you just
entered, then the read-only property is usually the culprit. Change the
property in windows explorer and repeat the bind to typedef process.
2) The second most common mistake is selecting the wrong copy of
"ni5640R FPGA VI Reference.ctl". Because the NI-5640R driver installs
support for both the NI PCI-5640R and the NI PXIe-5641R (as of my writing
this), there are a lot of copies of this control around your system. Make sure
you select the correct instance of this control, which is the copy that sits in
the same directory as the template VIs that are being used in your
project. Opening one of these VIs (the Configure Timebase for instance) and
selecting File>>Properties should tell you the path where the VI is
located.
3) Another mistake that I have seen in the past is people trying to use
the same set of template files for multiple different projects. When using
LabVIEW 2009 or older, each project should have its own copy of the template
VIs.
Also, it is strongly suggested that if you create any of your own
SubVIs that have FPGA Host Interface controls and indicators, those controls
and indicators should be bound to the same "ni5640R FPGA VI
Reference.ctl". This will ensure an easy upgrade/conversion should you
ever need to modify the control/indicator bitfile information in the future.
LabVIEW 2010 and the NI-5640R 1.5 driver (and later) contains a cool
new feature that makes this process no longer necessary.
If you are using LabVIEW 2010 (or newer):
In the past, the reason why you saw the broken wire between the
"Open FPGA VI Reference" and the first template VI was because of a
mismatch in the bitfile path in the two nodes. The NI-5640R 1.5 driver makes
use of a new feature in LabVIEW FPGA 2010 called the "Dynamic Host
Interface" that makes this no longer an issue. When you use the Dynamic
mode in the Open FPGA VI Reference node with Dynamic Host Interface controls
and indicators, you are no longer requiring that the downstream nodes
(controls, indicators, subVIs) have any specific information about the bitfile.
They instead contain only an interface of controls, indicators, FIFOs, etc. As
long as the wire coming into these nodes contains the necessary elements, the
wire will be unbroken. As opposed to having a separate copy of the template
stack for every project (like in the past) there is a single copy located at
“<LabVIEW folder>\instr.lib\ni5640R\Configuration\ni5640R Template.lvlib”
that has been converted to the dynamic host interface.
Detailed instructions for converting an existing (traditional host
interface) project to dynamic mode can be found in the help for the NI-5640R
1.5 driver (NI IF Transceivers Help). Try searching the help for “upgrade”. The quickest way to find the help file is to go to Start>>All Programs>>National Instruments>>NI-5640R>>Documentation.
If you do not want to convert your existing project to the Dynamic Host
Interface, but you still want to get the latest bug fixes and features, a copy
of the template that uses the traditional interface is located at “<LabVIEW
folder>\examples\instr\ni5640R\FPGA\Traditional Configuration” for your
convenience. This ni5640R Template.lvlib and the NI-5640R VIs subfolder can be
copied into your project.
Note: The Dynamic Host Interface eliminates the need to bind the Open
FPGA VI Reference to the "ni5640R FPGA VI Reference.ctl" typedef. It
is however suggested that if you create any of your own SubVIs that have FPGA
Host Interface controls and indicators, those controls and indicators should be
bound to your own typedef. This will make things simple should you ever need to
modify the control/indicator interface information in the future.
Note: You cannot mix Traditional FPGA Host Interface nodes with Dynamic
Host Interface nodes. For a specific Open FPGA VI Reference Node, all of the
downstream nodes that take in the interface wire must match the type of the
open reference node.
If I have not answered any of your questions feel free to post back.
-Dan
