crio

[crio]

hi,

this is valli again....

    my question was not about ADC but about DAC..... if i try to output a sine wave (analog signal)from the fpga to an oscilloscope and i send it to the DAC output port, will it be directly digitised by the board at that point and then reconvert it to the the analog signal at the output end or should my output be of the digitized form of the sine wave wen i feed it inot the DAC?????

can you please help me out????

Thank you

Valli

[JerryAL]

Hi Villi

I’m sorry, but your VI is so far from being able to run on the IF-RIO / NI 5640R that it really isn’t worth it to make it work.

If you want to get started on the IF-RIO, you must go and read both the “Getting Started with the NI PCI-5640R IF Transceiver and the LabVIEW FPGA Module” and the NI PCI-5640R Help file.

In addition, run through the Creating an FPGA Application section of the Getting Started guide.  This will lead to the generation of a signal that you can see on your oscilloscope.

If you do not have the installed documents, you can find them here in a zip file:
http://forums.ni.com/ni/board/message?board.id=ifrio&message.id=140

In addition, there are examples installed to help you get started.  Ones I have mentioned before.

Also, please confine your replies to the previous thread and not continue creating new threads on the Discussion Board.

Jerry

[crio]

hey jerry,

               The programs that are given as example code in the installation is driving me crazy..... it comes up with an error message saying no fpga target thoough the visa defines the resouce name and the vi is selected...... can u pls tell me why my program can never run on the PCi 5640r ???? i have attached my program with this mail

it would be really helpful if u can jus i can have an example code for simple signal generation on the fpga pci5640r .....please

thank you

valli

[JerryAL]

Hi Valli

Your VI will not run because it is missing too much programming components.  Code that controls the DAC as well as module timing.

The following images are from the ni5640R Input and Output example.

The following image shows the Configuration loop that is required in the FPGA for the module to generate a signal.  The controls need corresponding code in the Host VI.

This shows the generation part of the code.  In each iteration of the loop, and I or Q sample of I16 bit data is sent to the DAC for Digital Up Conversion.  The I and Q samples are interleaved.  The data to the DAC must be interleaved I and Q data samples.  No other method is supported.

So, your example is sending single sample data to the DAC which is not supported.  Also, you do not have a LabVIEW project (also required) or the Configuration loop and corresponding Host VI for control.  (also required.)

The only way to help you get started is for you to follow the Getting Started Guide, and when you get to a point some thing is not working, for us to help you work around that particular issue until you get up and running.

Jerry

Message Edited by Jerry_L on 11-03-2006 04:01 PM

[Elvinj]

Hi Jerry,

i would like to ask how to check and configure how many samples of data we can input to FIFO of the IFRIO. Is it configure in host vi or fpga vi?

for my case, i was input sampling rate of 1 MHz, 1000 samples signal to the IFRIO via 'Fill Output FIFO.vi' and the signal is clean but if i input more than 1000 samples, the output signal contain a lot of spurious.

Thanks.

[Elvinj]

I was input the psk signal to the IFRIO which is generate by the 'MT PSK transmitter.vi' from modulation tool kits.

Message Edited by ElvinJW on 12-15-2006 12:21 AM

[JerryAL]

Hi ElvinJW

Referring to the ni5640R Input and Output example.  A FPGA to Host FIFO (Input IQ) is created in the project and can be configured there as well for the size.

In addition, you can configure the FIFO size programmatically on the fly with an Invoke Method.  This is shown in the Host VI of the example as well.

From the LabVIEW Help:

Invoke Method Details

You can invoke the following FPGA Interface methods on most FPGA targets to control the FPGA VI. You might have fewer or more methods available depending on the FPGA target. Refer to the specific FPGA target hardware documentation for information about the FPGA Interface methods you can use.

FIFO - Displays one of the following methods you can use to read from or write to a Direct Memory Access (DMA) FIFO in the FPGA VI. FIFO is the name of the FIFO item in the project.

Configure - Allows you to specify the depth of the host memory part of the DMA FIFO. This method is optional.

Depth - specifies the number of elements in the host memory part of the DMA FIFO. If you do not wire this parameter, the Invoke Method function uses a default depth of twice the number of elements in the DMA FIFO item in the project. If you place the FIFO Configure method after a FIFO Start or FIFO Read method in the data flow, the Invoke Method function sets the new depth when the next FIFO Start or FIFO Read method executes.

Jerry