frequency synchronization problem

[rohit1986_xyz]

Hi,

I am using NI 5640R board. I have a VI to generate QAM samples which I am writing to the 5640R board and the o/p and i/p of the board are connected so that I can receive the data sent directly. I am using the example "ni5640R Input and Output" to receive the data. The problem is that the symbols received are not in phase with the symbols sent and I am unable to rectify this. This might be an old problem but being a new-commer, I am unable to understand and apply the solutions posted, to my case.

Please tell me how can I do frequency and time synchronization.

Thank you,

-Rohit.

[Vinay_Kumar]

Hi Rohit,

Seems like you are using the 5640R as a i/p and o/p device and not really programming the FPGA. For such kind of applications you can have a look at the examples using the NI-5640R instrument drivers and Modulation Toolkit (http://decibel.ni.com/content/docs/DOC-1710)

Can you also give me details regarding the symbol rate, carrier frequency, samples per symbol and the settings on the Tx and Rx (DAC/ ADC)?

Hope this helps!

Vinay

[rohit1986_xyz]

Thanx Vinay, I will look into it.

Symbol Rate is 500 KHz. Carrier frequency is 30 or 40 MHz (Tx n RX at the same frequency). Samples per symbol is 1. CIC interpolation factor = 25.

Clock Freq = 100MHz, DDC Decimation to 1MHz.

I guess thats it !! If you need  some more info, please let me know.

-Rohit

[Vinay_Kumar]

Hi Rohit,

By default the DAC uses 200MHz clock and the ADC uses 200MHz/2= 100MHz derived clock (I guess you are using the same setting).

Tx:

DAQ IQ Clk= 2* Refclk* clock multiplier/(4 * CIC) [refer to pg 8,9 of the getting started 5640r and LVFPGA manual.]

Based on the numbers you have mentioned,the math is as follows

DAQ IQ Clk= 2* 200MHz * 1/(4 *25)= 4MHz (I, Q interleaved)

Sampling rate= 2MS/s (one sample has an I and Q part)

Hence Samples per symbol = 2M/500k = 4( so generate 4 samples per symbol instead of 1 or change the CIC such that samples per symbol =1)

Rx:

Since the symbol rate= 500kHz, I guess you want to acquire at twice the symbol rate = 1MS/s.

Supported  decimation factor= 4, 8, 16,...1024

So, decimating 100MHz by 64=  1.5625MHz will be the sampling rate. So to achieve 1MS/s, you can do the following

1. either use external clock< 100MHz such that you can obtain 1MS/s using the suppported decimation factors

2. or perform resampling on PC/ host using IQ resampler in Modulation toolkit or  resample using the functions provided in labviews signal processing palette,

3. or change the symbol rate and redo the math

--Vinay