Hi,
I can have two clocks from my PCI5640R card. A DAC clock which I configured to run at 1MHz and a FPGA clock at 20MHz.
In another way of seeing it, my block can be eithered driven by a 1MHz clock or a 20MHz clock.
However, I want to my blocks driven by some other clock, say 5MHz. One reason might be that the code in my block is too complex to run at 20MHz. What kind of structure should I use? I attached the code I can think of ,but I do not know whether it really works the way I want. Say, will the content in the shiftregister be incremented every 0.2us, i.e., the increment and latch operation block driven by 5MHz?
It the code works, how does FPGA generate its 5MHz clock?
Moreover, what is the architecture of the attached code? by architecture, I mean the corresponding block diagram of a VHDL code which usually consists of counter, latch, adder or something.
Many Thanks.
David,