signal flow chart for using DIO on 5640R

[danhu2]

Hi,

There are a bunch of good templates to get me started with analog I/O but not for digital I/O. My project needs the host to send out a value through digital lines @10MHz. Now I have a few  basic questions regarding the standard procedures to work with DIO?

1. what are the essential items in the signal flow chart on host? Open session->configuration->write->initialization->close session?

2. What are the differences of opening a session using FPGA VI Reference.vi and 5640 init Generation Session.vi? They are not interchangable.

3. Do I have to use a FIFO to transfer data between FPGA and host in this case?

At last, I highly recommend ni group to create a working template for DIO. If easy modification to analog I/O template can work for DIO, please show to how, that'll be great.

Thank you.

Dan

[danhu2]

It's me again. I just realized that I'm using FPGA modules to program, not instrument driver. This answers my second question: FPGA Refence.vi is for FPGA module programming, the other one is for instrument driver programming.

I have two additional questions:

4. If the value to be sent is a 32-bit unsigned integer,  then it requires 5 cycle to output this value through the 7-pin port? Do I have to manually program this, or it's embedded in a ready-to-use vi?

5. Currently, I have no device to display the digital output nicely, is it possible to just check the voltage on each pin to verify that the pins are responding when I change to value to be sent?

Thanks,

Dan

[The_Red_Barron]

Hi Dan,

The basic flow of programming on the Host for digital output would be similar to:

Open FPGA Reference >> Configuration (as needed) >> Write to FPGA >> Close session

You could use a FIFO to pass data between the host and the FPGA or you could just pass data via controls and indicators.  I have included an example project which passes data from the host to a control on the FPGA VI.  If you are transferring the data as a 32-bit unsigned integer then you will need to manually format and control the way it is output from the FPGA VI.  There is not a pre-made function to do that.

As for testing, you can manually probe the pins on a connector with a DMM.  Here is the pinout for the AUX connector.

Regards,

Barron

[danhu2]

Barron, thanks for your quick reply. I can't open the attachment because it's Labview 2009 running on my computer. Can you take a screen shot of the block diagram?

Thanks.

Dan

[The_Red_Barron]

Hi Dan,

Here is a screenshot of the project explorer showing the DIO lines.  To add them to the project I right-clicked FPGA Target>>New>>FPGA I/O:

Here is the HOST VI:

Here is the FPGA VI:

Regards,