Hi David
The Read/Write Control programmatically runs from the top down. Setting the IQ sample to the FPGA, then the first Write IQ Sample to True and then the Write IQ Sample to False. On the FPGA the sample shows up first, (if the FPGA clock for the single cycle timed loop is running very slow, it’s possible that the setting arrive in the same loop iteration.) But nothing happens on the FPGA. The output from the lower left shift register is false, which goes to the not-input of the And gate, but the Write IQ is false until a True is sent down from the host. At that point, the input conditions of the And gate are satisfied, and a true comes out to put the IQ sample into the Dac 0 Data FIFO. On the next iteration of the loop, the output of the shift register is true, and to the not-input to become false, the Write IQ sample is probably still true, but we get a false from the And gate. No more data is stored into the Dac 0 Data FIFO. This will be the case as long as the Write IQ Control is true.
Eventually the Write IQ Sample goes false again, resetting the And gates function. When the Write IQ Sample goes true again, the next sample is written.
This sets up logic so that a sample is only written to the FIFO on a rising edge of the Write IQ Sample.
Jerry
