TNT4882 Back-to-Back Deassert Timing

[ppDev]

Figures 8 and 10 in the TNT4882 data sheet do not clearly show the chip timing requirements in order to perform back-to-back DMA or CPU reads or writes. Specifically:

1) What is the minimum time DACKN, RDN and WRN should be deasserted between back-to-back DMA accesses?

2) Also when using one-chip mode, what is the minimum time CSN, RDN, WRN must be deasserted between back-to-back CPU accesses?

3) The Generic Mode AC Characteristics table mentions “trr” but I can’t find this referenced in the timing diagrams. What is this?

[Steven_T]

Hello,

tRR is the minimum RDN unassertion time between back-to-back accesses.

 

For back-to-back write accesses, as long as the address setup time and minimum write pulse time are met then those timings should be sufficient

.

For back-to-back read accesses, tRR must be met in addition to address setup time and minimum read pulse width.

Minimum read and write pulse widths apply to both DMA and CPU accesses.

I hope this answers your questions,

Steven T.