Hello,
We are unable to send (and receive) data in DMA mode over GPIB from embedded application using TNT4882 (in generic pin configuration) and Motorola ColdFire MCF5307.
The programmed I/O including interrupt-driven programmed I/O works fine.
Before I go into details, let me sum up the problem in two sentences:
If I write a single 8-bit value to empty FIFO with DACK asserted after DRQ has been asserted, the FIFO is still empty (ISR3: NEF = 0, NFF = 1, INTSRC2 = 1). However, I am able to write 16 8-bit values into the FIFO with DACK asserted and read exactly the same values in correct (FIFO) order back with DACK asserted too.
Now the details:
The signals DACKN (TNT), DRQ (TNT), DREQ (MCF) and WRN (TNT) measured by oscilloscope correspond to the figure 10 ("DMA Write") in the TNT4882 ASIC data sheet (please see attached screenshots).
Because we don't have MCF DACK signal available, the DACKN signal is generated by CPLD on our GPIB board by AND operation of MCF chip select and A5 signals. It means that address space TNT-base ~ TNT-base+0x1F accesses the TNT in normal mode (CSN, A0-A4), while address space TNT-base+0x20 ~ TNT-base+0x20+0x1F accesses the TNT in DMA mode (DACK asserted).
Our embedded software is based on TNT 488.2 ESP-488TL package (one-chip mode). We are using 8-bit FIFO access only, though.
Here is a pseudo-code (that I'm using with my custom development toolkit app runnning on the target MCF5307) that simulates DMA controller transfer using normal CPU accesses ('#' denotes comment):
# the chip select setup (that works for programmed I/O):
[...]
# TNT chip initialization (that works for programmed I/O):
[...]
# TNT output setup:
W CMDR $08 # stop
W CMDR $10 # reset FIFO
W AUXMR $55 # clear END
W CMDR $10 # reset FIFO
# 4,096 (4Ki) bytes:
W CNT0 $00; W CNT1 $F0; W CNT2 $FF; W CNT3 $FF
W IMR0 $80 # nba
W AUXMR $F0 # AUXRJ: no timeout
W IMR1 $04 # ERR
W EOSR $00 # EOS character
W AUXMR $81 # AUXRA: HLDE
# DMA: DRQ unasserts after 14.9 us:
# CFG: TLCHLTE|CCEN|TMOE|TIM_BYTN; TIMER: $6A = 14.9 us
#W CFG $4E; W TIMER $6A
# - doesn't make a difference
# DMA: DRQ remains active (until FIFO is full)
# - burst mode (no duration limit):
# CFG: TLCHLTE|CCEN
#W CFG $48
# - doesn't make a difference
# DMA: DRQ unasserts after every DMA transfer - cycle
# steal mode:
# CFG: TLCHLTE|CCEN|TMOE; TIMER: $FF - unassert after
# 1 transfer
W CFG $4C; W TIMER $FF
W AUXMR $51 # HLDI
# FIFO/DRQ status before TNT transfer start:
R ISR3 # ISR3: INTSRC2: 0, NFF: 1, NEF: 0
# = FIFO empty
R STS1 # DRQ: 0
# start TNT transfer:
W CMDR $04 # GO
# FIFO/DRQ status after TNT transfer start, before
# first "DMA" cycle:
R ISR3 # INTSRC2: 1, NFF: 1, NEF: 0
# = FIFO ready, FIFO empty
R STS1 # DRQ: 1
# 1st "DMA" cycle - 1st byte:
# write to FIFOB (or any other location) in DMA addr
# space:
W FIFOB+$20 $11
R ISR3 # INTSRC2: 1, NFF: 1, NEF: 0
# = FIFO ready, FIFO empty
R STS1 # DRQ: 1
# - no data accepted into FIFO
# 2nd "DMA" cycle - 2nd byte:
# write to FIFOB (or any other location) in DMA addr
# space:
W FIFOB+$20 $22
R ISR3 # INTSRC2: 1, NFF: 1, NEF: 0
# = FIFO ready, FIFO empty
R STS1 # DRQ: 1
# - no data accepted into FIFO
# write rest of the FIFO:
W FIFOB+$20 $33
W FIFOB+$20 $44
W FIFOB+$20 $55
W FIFOB+$20 $66
W FIFOB+$20 $77
W FIFOB+$20 $88
W FIFOB+$20 $99
W FIFOB+$20 $AA
W FIFOB+$20 $BB
W FIFOB+$20 $CC
W FIFOB+$20 $DD
W FIFOB+$20 $EE
W FIFOB+$20 $FF
W FIFOB+$20 $00
W FIFOB+$20 $1E # 1 extra byte (not written to FIFO)
# The DRQ signal is now still asserted when writing
# with DACK asserted ("+$20").
# The DRQ signal is now unasserted when writing
# with DACK unasserted ("+$20" removed).
# read data written to FIFO back from offset 0:
# (DACK asserted, A0-4 ignored...)
R DIR+$20 # read value: $11
R DIR+$20 # read value: $22
R DIR+$20 # read value: $33
R DIR+$20 # read value: $44
R DIR+$20 # read value: $55
R DIR+$20 # read value: $66
R DIR+$20 # read value: $77
R DIR+$20 # read value: $88
R DIR+$20 # read value: $99
R DIR+$20 # read value: $AA
R DIR+$20 # read value: $BB
R DIR+$20 # read value: $CC
R DIR+$20 # read value: $DD
R DIR+$20 # read value: $EE
R DIR+$20 # read value: $FF
R DIR+$20 # read value: $00
R DIR+$20 # read value: $11 # 1 extra byte
# (same as 1st value)
When doing the same write to FIFO directly with DMA controller, the DMA transfer successfully finishes (DRQ keeps asserting after every byte transferred by DMA controller), but no data are transferred over GPIB bus when tried to read the data from a PC. The TNT count registers do not indicate any transfer either (of course).
When doing the same write to FIFO using PIO address space (i.e. the same pseudo-code above with "+$20" removed), those 16 bytes written to FIFO are transferred to a PC just fine. When the FIFO is full, the ISR3:NFF is set to 0 and DRQ is unasserted.
Do you happen to know where could be the problem ?
Thank you for your time.
--
Radomir Tomis
ELCOM, a.s., Division of Virtual Instrumentation
Radomir.Tomis@dvi.elcom.cz
http://dvi.elcom.cz/english
