tnt5002 gen4882 mode write timing

[powie]

Hi,

I'm using the TNT5002 in GEN4882 mode.  I can read all registers just fine but don't seem to be able to write to them.  I'm using the exact same firmware (in C) I've used several times before on other designs.  I've checked the compiled assembly language and it looks just fine (nothing optimized out!) The only hardware difference in this design is the timing of the CS# and WR# signals.  In the other designs they were coincident (i.e. asserted and unasserted together) whereas in this design I'm using the "raw" CS# and R/W# signals from a ColdFire so the WE# signal is asserted 10ns before CS# is asserted and unasserted 10ns after CS# is unasserted.  I would not have thought this made any difference - but maybe I'm wrong!  I would have thought that you use the logical OR of these two signals (just like for the CS# and OE# signals).

After initializing the TNT5002 the ADR0 register does not have the address written but instead it contains 0, I have tried writing several different data to no avail.

Any ideas?

Paul Withers

[Steven_T]

Hello Powie,

From looking at the timing diagrams for GEN4882 mode, I see that behavior you are describing is exactly what is pictured.  No maximum clock period is given for this interaction.  For reference, what is the frequency of the clock you are using with the TNT5002?

Have you checked the other timing diagrams to make sure that you are not violating any of the specifications?  The timing specifications start on page A-6 of the TNT5002 Technical Reference Manual.

Thanks,

Steven T.

[powie]

Thanks for the reply.  Actually I've found the solution over the weekend.  The ColdFire does not unassert the WR line between consecutive writes to the same address, but it does unassert the CS line.  It seems that the TNT5002 needs the WR to unassert between each write.  I've temporarily fixed it by doing a dummy read of the ADR0 register immediately after every write to any TNT5002 register.  Other than that it doesn't mind WR being asserted before CS or unassert after CS.  As it happens, on the four previous designs I've done using the TNT5002 this doesn't happen.

In practice I'll have to change the hardware to add an OR gate in series with the WR line to the TNT5002, gating it with the CS line, to ensure that the WR line unasserts between accesses.  It sure would have been nice if NI had put it in the IC though!

Thanks,

Paul Withers