02-08-2017 12:45 AM
Hi Jenny,
Have you made any changes to the code you posted before? If so did anything improve? If not then please try changing the number of channels input to the resampler. This will definitely cause some issues.
02-08-2017 05:53 AM
Hi James,
You are right to put the enum to 7 and ensure consistency between the input to the FIFO and the output. We have finally made some progress. The problem stems from the fact that the example is written for a 4ch current module, we have a 3ch. So we originally deleted the CT neutral from the example and (eventually) changed the enum to 6, which made the FPGA correct, but the RT was wrong still.
Now we have used the neutral voltage as the input to the CT neutral in the original example, so we have forced it to 7 input channels. This makes both the FPGA and RT work. At least now the frequency is the same on both and corresponds to something like UK grid frequency!
One last bugbear is that the RT voltage is +/- 630v pk-pk, 470Vrms.