Can CLIP FPGA component include Xilinx Coregen FIFO?

[golson]

I would like to create a VHDL design that will be able to write to a fifo to capture data then send the data to

the Labview components downstream.  Is it possible to include the Xilinx FIFO component in the design using

a CLIP?

[RyanB]

Yes, I have included Coregen FIFO's in a CLIP, however I found it easier to use LV FPGA FIFO's instead.

-RB

[golson]

How can I interface the FIFO and following VHDL Logic to labview FPGA. 
Any help is appreciated.

[David_L]

Can you give more detail to your question?

[golson]

The Example of CLIP is very simple and only contains one VHDL file with some simple low level logic.  I have a hierarchical design that needs to access

data from a FIFO.  I might try to include a VHDL design (including a FIFO) that will be part of a CLIP node.  I would need labview to write to the FIFO and the VHDL code could read the data bytes out of the FIFO as required by the VHDL (CLIP design).  This design is similar to a UART except there is an additional ready signal and clock.  this design uses a parallel to serial converter similar to a UART. 

The FIFO created by xilinx will include a VHDL file that I used in simulation.  But when creating a FPGA using XST I would need to add to a project

the XCO file and not add the FIFO VHDL file.  The XCO file is enough to create the FIFO in the design in XST.

But with Labview how do I include the FIFO XCO file in a CLIP?

Right now I have not figured out everything about interfacing the FIFO also.  But I guess it is simply creating DATA, WR_EN, signals in Labview and reading the FULL flag to write the data into the FIFO.

We have created the interface using pure labview.  But we have some timing problems or logic problems causing the wrong signal waveforms.

That is one reason why I have been looking into CLIP.

Thank You,

 Gary

Message Edited by golson on 06-22-2009 12:51 PM

[David_L]

Sorry for taking so long to get back here, I had to go talk to more knowledgable people than I.  It turns out you cannot directly add an XCO file to your CLIP node, however you can compile the XCO core down to the netlist form (using Xilinx tools) and then add the NGC file to the CLIP.  This should accomplish the same thing that you want to do with the XCO file.